Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Document Table of Contents

2.2.1. Input Register Bank for Floating-point Arithmetic

The input register banks for floating-point DSP blocks are available for the following input signals:
  • fp32_adder_a
  • fp32_adder_b
  • fp32_mult_a
  • fp32_mult_b
  • fp16_mult_top_a
  • fp16_mult_top_b
  • fp16_mult_bot_a
  • fp16_mult_bot_b
  • Dynamic ACCUMULATE control signal
Figure 10. Location of Input Register for FP32 Operation Modes
Figure 11. Location of Input Register for FP16 Operation Modes

All the registers in the DSP blocks are positive-edge triggered. These registers are not reset after power up and may hold unwanted data. Assert the CLR signal to clear the registers before starting an operation.

Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.

The following variable precision DSP block signals control the input registers within the variable precision DSP block:
  • CLK
  • ENA[2..0]
  • CLR[0]