Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Document Table of Contents

2.2.2. Pipeline Registers for Floating-point Arithmetic

Floating-point arithmetic has 3 latency layers of pipeline registers. You can bypass all latency layers of the pipeline registers or use any one, two or three layers of pipeline registers.

Figure 12. Location of Pipeline Register for FP32 Operation Modes
Figure 13. Location of Pipeline Register for FP16 Operation Modes
The following variable precision DSP block signals control the pipeline registers within the variable precision DSP block:
  • CLK
  • ENA[2..0]
  • CLR[1]