Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Document Table of Contents

3.1.5. Systolic FIR Mode

The basic structure of a FIR filter consists of a series of multiplications followed by an addition.

Figure 23. Basic FIR Filter Equation

Depending on the number of taps and the input sizes, the delay through chaining a high number of adders can become quite large. To overcome the delay performance issue, the systolic form is used with additional delay elements placed per tap to increase the performance at the cost of increased latency.

Figure 24. Systolic FIR Filter Equivalent Circuit

Intel Agilex® 7 variable precision DSP blocks support the following systolic FIR structures:

  • 18-bit
  • 27-bit

In systolic FIR mode, the input of the multiplier can come from four different sets of sources:

  • Two dynamic inputs
  • One dynamic input and one coefficient input
  • One coefficient input and one pre-adder output
  • One dynamic input and one pre-adder output