Intel Agilex® 7 Variable Precision DSP Blocks User Guide

ID 683037
Date 10/02/2023
Document Table of Contents

6.2.4. Double Accumulator

The double accumulator feature adds an additional register in the accumulator feedback path that process the interleaved complex data (I, Q) . The double accumulator register follows the output register, which includes the clock, clock enable, and aclr. The additional accumulator register returns result with a one-cycle delay. This feature enables you to have two accumulator channels with the same resource count.

The following figure shows the double accumulator implementation.

Figure 67. Double Accumulator