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1. Intel Agilex® 7 Variable Precision DSP Blocks Overview
2. Intel Agilex® 7 Variable Precision DSP Blocks Architecture
3. Intel Agilex® 7 Variable Precision DSP Blocks Operational Modes
4. Intel Agilex® 7 Variable Precision DSP Blocks Design Considerations
5. Native Fixed Point DSP Intel Agilex® FPGA IP Core References
6. Multiply Adder Intel® FPGA IP Core References
7. ALTMULT_COMPLEX Intel® FPGA IP Core References
8. LPM_MULT Intel® FPGA IP Core References
9. LPM_DIVIDE Intel® FPGA IP Core References
10. Native Floating Point DSP Intel Agilex® FPGA IP References
11. Intel Agilex® 7 Variable Precision DSP Blocks User Guide Archives
12. Document Revision History for the Intel Agilex® 7 Variable Precision DSP Blocks User Guide
2.1.1. Input Register Bank for Fixed-point Arithmetic
2.1.2. Pipeline Registers for Fixed-point Arithmetic
2.1.3. Pre-adder for Fixed-point Arithmetic
2.1.4. Internal Coefficient for Fixed-point Arithmetic
2.1.5. Multipliers for Fixed-point Arithmetic
2.1.6. Adder or Subtractor for Fixed-point Arithmetic
2.1.7. Accumulator, Chainout Adder, and Preload Constant for Fixed-point Arithmetic
2.1.8. Systolic Register for Fixed-point Arithmetic
2.1.9. Double Accumulation Register for Fixed-point Arithmetic
2.1.10. Output Register Bank for Fixed-point Arithmetic
2.2.1. Input Register Bank for Floating-point Arithmetic
2.2.2. Pipeline Registers for Floating-point Arithmetic
2.2.3. Multipliers for Floating-point Arithmetic
2.2.4. Adder or Subtractor for Floating-point Arithmetic
2.2.5. Output Register Bank for Floating-point Arithmetic
2.2.6. Exception Handling for Floating-point Arithmetic
3.2.2.1. FP16 Supported Precision Formats
3.2.2.2. Sum of Two FP16 Multiplication Mode
3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode
3.2.2.4. Sum of Two FP16 Multiplication with Accumulation Mode
3.2.2.5. FP16 Vector One Mode
3.2.2.6. FP16 Vector Two Mode
3.2.2.7. FP16 Vector Three Mode
5.1. Native Fixed Point DSP Intel Agilex® FPGA IP Release Information
5.2. Supported Operational Modes
5.3. Maximum Input Data Width for Fixed-point Arithmetic
5.4. Maximum Output Data Width for Fixed-point Arithmetic
5.5. Parameterizing Native Fixed Point DSP IP
5.6. Native Fixed Point DSP Intel Agilex® FPGA IP Signals
5.7. IP Migration
10.1. Native Floating Point DSP Intel Agilex® FPGA IP Release Information
10.2. Native Floating Point DSP Intel Agilex® FPGA IP Core Supported Operational Modes
10.3. Parameterizing the Native Floating Point DSP Intel Agilex® FPGA IP
10.4. Native Floating Point DSP Intel Agilex® FPGA IP Core Signals
10.5. IP Migration
10.4.1. FP32 Multiplication Mode Signals
10.4.2. FP32 Addition or Subtraction Mode Signals
10.4.3. FP32 Multiplication with Addition or Subtraction Mode Signals
10.4.4. FP32 Multiplication with Accumulation Mode Signals
10.4.5. FP32 Vector One and Vector Two Modes Signals
10.4.6. Sum of Two FP16 Multiplication Mode Signals
10.4.7. Sum of Two FP16 Multiplication with FP32 Addition Mode Signals
10.4.8. Sum of Two FP16 Multiplication with Accumulation Mode Signals
10.4.9. FP16 Vector One and Vector Two Modes Signals
10.4.10. FP16 Vector Three Mode Signals
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4.2.1.2. FP16 Operation Mode Supported Register Configurations
Latency | Data Input Register | Multiplier 1st Pipeline Register | Multiplier 2nd Pipeline Register | Adder Input Register | Adder Pipeline Register | Output Register |
---|---|---|---|---|---|---|
fp16_mult_input_clken | mult_pipeline_clken | mult_2nd_pipeline_clken | adder_input_clken | adder_pl_clken | output_clken | |
0 | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Enable | Disable | Disable | Disable | Disable | Disable |
1 | Disable | Disable | Disable | Disable | Disable | Enable |
2 | Enable | Disable | Disable | Disable | Disable | Enable |
3 | Enable | Disable | Disable | Enable | Disable | Enable |
4 | Enable | Disable | Disable | Enable | Enable | Enable |
≥5 | Enable | Disable, enable | Enable | Enable | Enable | Enable |
Latency | Data Input Register | Adder 1st Pipeline Register | Adder 2nd Pipeline Register | Multiplier 1st Pipeline Register | Multiplier 2nd Pipeline Register | Adder Input Register | Adder Pipeline Register | Output Register | |
---|---|---|---|---|---|---|---|---|---|
fp32_adder_a_clken | fp16_mult_input_clken | fp32_adder_a_chainin_pl_clken | fp32_adder_a_chainin_2nd_pl_clken | mult_pipeline_clken | mult_2nd_pipeline_clken | adder_input_clken | adder_pl_clken | output_clken | |
0 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
2 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
≥3 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Disable | Enable |
≥4 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Enable |
≥5 | Enable | Enable | Disable, enable | Disable, enable | Disable, enable | Enable | Enable | Enable | Enable |
Latency | Data Input Register | Adder 1st Pipeline Register | Adder 2nd Pipeline Register | Multiplier 1st Pipeline Register | Multiplier 2nd Pipeline Register | Adder Input Register | Adder Pipeline Register | Output Register | ||
---|---|---|---|---|---|---|---|---|---|---|
accumulate_clken | fp16_mult_input_clken | accum_pipeline_clken | accum_2nd_pipeline_clken | mult_pipeline_clken | mult_2nd_pipeline_clken | accum_adder_clken | adder_input_clken | adder_pl_clken | output_clken | |
1 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
2 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
≥3 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Disable | Enable |
≥4 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Enable | Enable |
≥5 | Enable | Enable | Disable, enable | Disable, enable | Disable, enable | Enable | Enable | Enable | Enable | Enable |
Latency | Data Input Register | Adder 1st Pipeline Register | Adder 2nd Pipeline Register | Multiplier 1st Pipeline Register | Multiplier 2nd Pipeline Register | Adder Input Register | Adder Pipeline Register | Output Register | |
---|---|---|---|---|---|---|---|---|---|
fp32_adder_a_clken | fp16_mult_input_clken | fp32_adder_a_chainin_pl_clken | fp32_adder_a_chainin_2nd_pl_clken | mult_pipeline_clken | mult_2nd_pipeline_clken | adder_input_clken | adder_pl_clken | output_clken | |
0 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
2 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
≥3 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Disable | Enable |
≥4 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Enable |
≥5 | Enable | Enable | Disable, enable | Disable, enable | Disable, enable | Disable, enable | Enable | Enable | Enable |
Latency | Data Input Register | Adder 1st Pipeline Register | Adder 2nd Pipeline Register | Multiplier 1st Pipeline Register | Multiplier 2nd Pipeline Register | Adder Input Register | Adder Pipeline Register | Output Register | |
---|---|---|---|---|---|---|---|---|---|
fp32_adder_a_clken | fp16_mult_input_clken | fp32_adder_a_chainin_pl_clken | fp32_adder_a_chainin_2nd_pl_clken | mult_pipeline_clken | mult_2nd_pipeline_clken | adder_input_clken | adder_pl_clken | output_clken | |
0 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Disable |
1 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
2 | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
≥3 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Enable |
≥4 | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Enable |
Latency | Data Input Register | Adder 1st Pipeline Register | Adder 2nd Pipeline Register | Multiplier 1st Pipeline Register | Multiplier 2nd Pipeline Register | Adder Input Register | Adder Pipeline Register | Output Register | |||
---|---|---|---|---|---|---|---|---|---|---|---|
accumulate_clken | fp32_adder_a_clken | fp16_mult_input_clken | accum_pipeline_clken | accum_2nd_pipeline_clken | mult_pipeline_clken | mult_2nd_pipeline_clken | accum_adder_clken | adder_input_clken | adder_pl_clken | output_clken | |
1 | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
2 | Enable | Enable | Enable | Disable | Disable | Disable | Disable | Disable | Disable | Disable | Enable |
≥3 | Enable | Enable | Enable | Disable, enable | Disable, enable | Disable | Disable | Enable | Enable | Enable | Enable |
≥4 | Enable | Enable | Enable | Disable, enable | Disable, enable | Disable, enable | Enable | Enable | Enable | Enable | Enable |