AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

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ID 683012
Date 12/31/2019
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Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.3.1. SDI Reclock

Figure 13. SDI Reclock Block Diagram
The SDI reclock control logic configures the counter settings to adjust the fPLL output clock in real time without reconfiguring the entire FPGA device. In an environment without an external VCXO, the PLL reconfiguration controller needs to configure only the M counter fractional value (K or Mfrac) for the delta-sigma modulator.
Note: After you perform the reconfiguration, you must recalibrate.

The Intel® Arria® 10 fPLL has a delta sigma fPLL architecture that allows integer and fraction multiplications for the output frequency. The delta-sigma modulator shifts the fractional noise to high frequencies and the PLL filters out the noise. The fPLL uses divide counters and different VCO taps to perform frequency synthesis and phase shift. You need an external lock detection IP logic for a reliable lock detection of the fPLL when it is operating in SDI direct mode.

The reclock control logic generates the Mfrac value during runtime based on the incoming reference signals: horizontal sync value pulse (HSYNC), frame lock status, TRS lock status, incoming video standard, and rx_clkout_is_ntsc_paln. The HSYNC signal is extracted from the incoming video stream and the feedback signal, which is the divided value of the TX and RX clock out.

For more details, refer to the reclock source codes in the reference design.

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