AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

Download PDF
ID 683012
Date 12/31/2019
Public
Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design Hardware and Software Requirements Connecting the Development Board to the Cable Driver Setting the DIP Switches Connecting the Hardware to the Power Supplies Port Assignments 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design

Complete the steps in the following topics to set up the required hardware for triple rate SDI II VCXO removal reference design.

Hardware and Software Requirements

The triple rate SDI II VCXO removal reference design requires the following hardware and software:

  • Intel® Arria® 10 GX FPGA Development Board (10AX115S3F45E2SGE3)
  • BNC plug to SMB plug cables
  • SDI Signal Analyzer
  • SDI Signal Generator
  • Intel® Quartus® Prime version 16.0

Connecting the Development Board to the Cable Driver

Connect the J20 (RX port) to external video source and the J21 (TX port) to video scope using BNC plug to SMB plug cables.

Figure 9. Hardware Connection

Setting the DIP Switches

Set the DIP switches of the development board as specified in the following table.

Table 5.  DIP Switch Control Settings
DIP Switch Schematic Signal Name Description Setting
SW3

(PCIe*)

 1 X1 ON for PCIe X1 ON
2 X4 ON for PCIe X4 ON
3 X8 ON for PCIe X8 ON
4 — OFF for 1.35 V MEM_VDD power rail OFF
SW4

(JTAG)

 1 Arria 10 OFF to enable the Intel® Arria® 10 device in the JTAG chain OFF
2 MAX V OFF to enable the MAX V device in the JTAG chain OFF
3 FMCA ON to bypass the FMCA connector in the JTAG chain ON
4 FMCB ON to bypass the FMCB connector in the JTAG chain ON
SW5

(Configuration)2

1 MSEL0 ON for MSEL0 = 1; for FPP standard mode OFF
2 MSEL1 ON for MSEL1 = 0; for FPP standard mode OFF
3 MSEL2 ON for MSEL2 = 0; for FPP standard mode ON
4 VIDEN OFF for enabling VID_EN for the Smart Voltage ID (SmartVID) feature ON
SW6

(Board Settings)

1 CLK_SEL

ON for 100 MHz on-board clock oscillator selection

OFF for SMA input clock selection

 ON
2 CLK_EN OFF for setting CLK_ENABLE signal high to the MAX V device OFF
3 Si516_FS

ON for setting the SDI REFCLK frequency to 148.35 MHz

OFF for setting the SDI REFCLK frequency to 148.5 MHz

 OFF
4 FACTORY

ON to load factory image from flash

OFF to load user hardware from flash

 ON
5 RZQ_B2K

ON for setting RZQ resistor of Bank 2K to 99.17 ohm

OFF for setting RZQ resistor of Bank 2K to 240 ohm

 OFF
Figure 10. DIP Switches


Connecting the Hardware to the Power Supplies

Connect the development board to the 12V DC input (J13) power supply.

Port Assignments

When you set up the hardware, the following physical ports are assigned to the SDI channels.

Table 6.  SDI Channels and Ports
SDI Channel Hardware RX Port TX Port
0 Arria 10 GX development board SDI_RX_P (J20) SDI_TX_P (J21)
2 Set the MSEL [2:0] bits according to your chosen configuration scheme.
Level Two Title