AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

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ID 683012
Date 12/31/2019
Public
Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.4. Compiling the Design and Configuring the FPGA

You must compile the design before you can configure the FPGA. Because the design is volatile, you must reload the design each time you power on the board.

Follow these steps to compile the design and configure the Arria 10 device:

  1. To test the reference designs targeted on Intel® Arria® 10 device, download the reference design file to your local project directory:
    • Triple Rate SDI II with External VCXO reference design: sdi_tr_a10_es3_vcxo_an746.par
    • Triple Rate SDI II VCXO Removal reference design:sdi_tr_a10_es3_vcxoless_an746.par
  2. Launch the Intel® Quartus® Prime software.
  3. On the File menu, click New Project Wizard.
  4. On the New Project Wizard page, open Design Template Installation. Select the design template you want to install. Click Next, then Finish.
  5. On the Processing menu, click Start Compilation.
  6. Before you begin the FPGA configuration, ensure that the Intel® Quartus® Prime Programmer and the Intel® FPGA Download Cable II driver are installed on the host computer, the board is powered, and no other applications that use the JTAG chain are running.
  7. Connect the USB cable to the board.
  8. On the Tools menu, click Programmer.
  9. Click Auto Detect to display the devices in the JTAG chain and select a device.
  10. Right click and select Change File. Then, select the appropriate .sof file from the project directory and click Open.
    • Triple Rate SDI II with External VCXO reference design: sdi_tr_a10_vcxo.sof
    • Triple Rate SDI II VCXO Removal reference design: sdi_tr_a10_vcxoless.sof
  11. Turn on the Program/Configure option for the .sof file.
  12. Click Start to download the .sof file to the FPGA. Configuration is complete when the progress bar reaches 100%.
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