SDI II Intel FPGA IP

• Channel 0—the instance of the SDI II IP in this channel is configured to support full-duplex operations and the triple-rate video standards, SD-SDI, HD-SDI, and 3G-SDI.

  The SDI II receiver, TX PLL, and TX transceiver PHY reset controller use the 148.5 MHz/148.35 MHz external clock source from the VCXO (si516) block on the development board. The RX data is looped back to the transmitter through a FIFO buffer. The interface is configured to operate at 270 Mbps, 1.485/1.4835 Gbps, or 2.97/2.967 Gbps.

• Channel 1—the instance of the SDI II IP is configured as a transmitter that supports the triple-rate video standards, SD-SDI, HD-SDI, and 3G-SDI. This instance acts as a video source, and transmits video stream at 270 Mbps (SD), 1.485/1.4835 Gbps (HD), or 2.97/2.967 Gbps (3G) through the transceiver TX pins. The video pattern generator provides the input to this instance.

The Intel® Arria® 10 fPLL and Intel® Arria® 10 Transceiver CMU PLL IPs. The Intel® Arria® 10 reference design version 16.0 uses one CMU and one fPLL core as the TX PLL for the Intel® Arria® 10 Transceiver Native PHY IP.

These IP cores use 148.5/148.35 MHz from external VCXO as a reference clock frequency for channel 0 TX PLL and default 270 MHz from Si5338 Programmable Oscillator as a reference clock frequency for channel 1 TX PLL.

The phase frequency detector (PFD) block controls the external clock source from the VCXO (si516) block on the development board to minimize the difference in PPM between the data rates of the receiver and transmitter. This control is required to prevent data overflow or underflow.

The video pattern generator produces the color bar or pathological test patterns. You can configure the color bar as 100% or 75% amplitude. The color bar pattern is the preferred pattern for image generation. You can use the pathological pattern to stress the PLL and cable equalizer of the attached video equipment. You can configure this video pattern generator to generate various video formats at SD/HD/3G rates.

A simple logic to generate a slow clock and display on the LEDs.

The SDI II IO core.

Channel 0—the instance of the SDI II IP in this channel is configured in simplex mode and support SD-SDI, HD-SDI, and 3G-SDI.

This channel demonstrates a receiver-to-transmitter loopback by decoding, buffering and retransmitting the received data to be displayed on video scope. The received data comes from an external signal generator.

The SDI II receiver uses an external clock 148.5 Mhz. A SDI reclocking soft logic is to retune the fPLL output clock. The generated low jitter output clock (148.5 or 148.35 MHz) of the fPLL is directly supplied to the transceiver input clock.

The Arria 10 fPLL IP core.

This reference design uses an fPLL core as the TX PLL for the Arria 10 Transceiver Native PHY IP core. It uses default 100 MHz from Si5338 Programmable Oscillator as the reference clock frequency for TX PLL.

A simple logic to generate a slow clock and display on the LEDs.

A soft encrypted IP logic to provide a reliable lock detection of the fPLL.

The Arria 10 Transceiver Native PHY IP core. The reference design uses this PHY IP core to configure the transceiver PHY for the SDI II protocol implementation. You can select the preset settings for the PHY IP core defined for the SDI II protocol. To apply a preset to the PHY IP core, double click the preset name. When you apply a preset, the PHY parameters are set accordingly for the instance. For example, selecting the SDI 3G PAL preset enables all parameters and ports for the 3G-SDI single rate (TX and RX) and triple rate TX with the data rate factor of 1/1 and configured in duplex mode. You may change the direction based on your design needs.

The Transceiver PHY Reset Controller IP core. This reset controller handles the sequencing of the transceiver reset. Depending on the status received from the transceiver PHY, TX PLL, or the reset input, the reset controller generates the TX or RX reset signals to the transceiver PHY and TX PLL.

This block contains a dual-clock FIFO (DCFIFO) buffer to handle the data transmission across asynchronous clock domains—the receiver recovered clock and transmitter clock out. The receiver sends the decoded RX data to the transmitter through this FIFO buffer. When the receiver is locked, the RX data is written to the FIFO buffer. The transmitter starts reading, encoding, and transmitting the data when half of the FIFO buffer is filled.

This block contains a state machine that performs the transceiver reconfiguration process. The Avalon-MM reconfiguration interface of this block is connected to the Arria 10 Transceiver Native PHY for the reconfiguration of the SDI II IP core. Although this block supports both TX and RX reconfiguration, this reference design only implements the RX reconfiguration.