AN 746: SDI II Triple-Rate Reference Designs for Intel® Arria® 10 Devices

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ID 683012
Date 12/31/2019
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Document Table of Contents
Document Table of Contents x
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices x
1.1. Triple Rate SDI II with External VCXO Reference Design 1.2. Triple Rate SDI II VCXO Removal Reference Design 1.3. Reference Design Components 1.4. Compiling the Design and Configuring the FPGA 1.5. Document Revision History
1.1. Triple Rate SDI II with External VCXO Reference Design x
1.1.1. Setting up the Hardware for Triple Rate SDI II with External VCXO Reference Design 1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design Reset
1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design x
Reset 1.1.2.1. Test Pattern Transmitter 1.1.2.2. Receiver 1.1.2.3. Serial Loopback 1.1.2.4. Parallel Loopback
1.2. Triple Rate SDI II VCXO Removal Reference Design x
1.2.1. Setting up the Hardware for Triple Rate SDI II VCXO Removal Reference Design 1.2.2. Running the SDI II VCXO Removal Reference Design
1.2.2. Running the SDI II VCXO Removal Reference Design x
1.2.2.1. Receiver 1.2.2.2. Parallel Loopback
1.3. Reference Design Components x
1.3.1. SDI Reclock
1. Triple Rate SDI II Reference Designs for Intel® Arria® 10 Devices

1.1.2. Running the Triple Rate SDI II with External VCXO Reference Design

When the board is set up and the FPGA is configured, you can start running the demonstration tests. Subsequent topics describe the tests that you can run.

Table 3.  DIP SwitchUse the SW2 DIP switches to specify the input and output type for the tests. A logical 0 indicates that the switch is ON; a logical 1 indicates that the switch is OFF.
SW2 Description
8
  • 0: 75% color bars
  • 1: 100% color bars
7
  • 0: Output color bars
  • 1: Output pathological
6
  • 0: Output color
  • 1: Output no color
5 Unused
4:1
  • 0000: SD – 525i59.94
  • 0001: SD – 625i50
  • 0010: HD – 1080i60
  • 0011: HD – 1080i50
  • 0100: HD – 1080p24
  • 0101: HD – 720p60
  • 0110: HD – 720p30
  • 0111: HD – 1080p30
  • 1000: HD – 1080p25
  • 1001: 3Ga – 1080p60
  • 1010: 3Ga – 1080p50
  • 1011: 3Gb – 2x1080i60
  • 1100: 3Gb – 2x720p30
  • 1101: 3Gb – 2x1080p30
  • 1110: 3Gb – 1080p60
  • 1111: 3Gb – 1080p50

Table 4.  User LEDsThe User LEDs indicate the expected results. A logical 1 indicates that the LED illuminates, a logical 0 indicates otherwise.
User LEDs Description
D3 The heartbeat of the transmitter clock out for channel 0.
D4 The heartbeat of the receiver recovered clock out for channel 0.
D5 Frame locked for channel 0.
D6 TRS locked for channel 0.
D7, D8 RX signal standard for channel 0:
  • SD: [D7, D8]=00
  • HD: [D7, D8]=01
  • 3Ga: [D7, D8]=11
  • 3Gb: [D7, D8]=10
D9, D10 Internal pattern generator signal standard for channel 1:
  • SD: [D9, D10]=00
  • HD: [D9, D10]=01
  • 3Ga: [D9, D10]=11
  • 3Gb: [D9, D10]=10
Note: You need to compile and configure the design before you run the tests. For more information about compiling and configuring the design, refer to Compiling the Design and Configuring the FPGA.

Reset

You may reset the reference design by pressing the S4 push button on the development board.

Level Two Title