This reference design consists of two channels: channel 0—SDI II IP in duplex mode and channel 1—SDI II IP configured as a transmitter. In Intel® Arria® 10 devices, the transceiver is no longer part of the SDI II IP and the TX PLL is separated from the transceiver PHY.
Figure 1. Triple Rate SDI II with External VCXO Reference Design Block DiagramThis figure shows a high-level block diagram of the triple rate SDI II VCXO reference design.
Note: The Intel® Arria® 10 Transceiver Native PHY IP does not provide the SDI triple rate duplex preset option because only RX requires dynamic reconfiguration. Multiple profiles in duplex mode may include some TX registers that are not necessary. The multiple profiles for HD-SDI and 3G-SDI are provided in the SDI triple rate RX preset for dynamic reconfiguration. The Intel® Arria® 10 Native PHY (RX) IP is added in the Intel® Quartus® Prime project to include the *_CFG0.sv and **_CFG1.sv files for the SDI triple rate duplex reconfiguration to function properly.
For more information about each component in the block diagram, refer to Reference Design Components.