Power and Thermal Analyzer User Guide

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ID 865226
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Power and Thermal Analyzer 2. Estimating Power Consumption with the Power and Thermal Analyzer 3. Power and Thermal Analyzer (PTA) Graphical User Interface 4. Power and Thermal Analyzer Resource Types 5. Command Line Options and Scripting 6. Factors Affecting the Accuracy of the Power and Thermal Analyzer 7. Document Revision History for the Power and Thermal Analyzer User Guide A. Measuring Static Power B. Tcl Command Reference
1. Overview of the Power and Thermal Analyzer x
1.1. Accessing the Power and Thermal Analyzer 1.2. PTA Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Power and Thermal Analyzer x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
3. Power and Thermal Analyzer (PTA) Graphical User Interface x
3.1. PTA - Device Selector Dialog Box 3.2. PTA - Primary GUI Components 3.3. PTA - Hierarchical Design Editor 3.4. PTA - Using Design Hierarchies in the Power and Thermal Analyzer 3.5. PTA - Entering Hierarchy Information Into the PTA 3.6. PTA - Current Drawn per Supply Tab 3.7. PTA - Temperature and Cooling Tab 3.8. PTA - Resource Utilization Panel 3.9. PTA - Register Dynamic Power in Agilex Devices 3.10. PTA - Input Fields 3.11. PTA - Data Entry Error Messages 3.12. PTA - Search Features 3.13. PTA - Filtered Searches 3.14. PTA - Using the Tcl Console to Perform Searches
4. Power and Thermal Analyzer Resource Types x
4.1. PTA - Power Summary 4.2. PTA - Root Entry 4.3. PTA - Instance 4.4. PTA - Logic Resource Type 4.5. PTA - RAM Resource Type 4.6. PTA - DSP Resource Type 4.7. PTA - Clock Resource Type 4.8. PTA - PLL Resource Type 4.9. PTA - I/O Resource Type 4.10. PTA - Transceiver Resource Type 4.11. PTA - Crypto Resource Type 4.12. PTA - NOC Resource Type 4.13. PTA - HBM Resource Type
4.10. PTA - Transceiver Resource Type x
4.10.1. PTA - Estimating E-Tile Channel PLL Power
5. Command Line Options and Scripting x
5.1. Invoking the Power and Thermal Analyzer from the Command Line 5.2. Running Scripts with the Power and Thermal Analyzer
6. Factors Affecting the Accuracy of the Power and Thermal Analyzer x
6.1. Toggle Rate 6.2. I/O Bank Allocation
B. Tcl Command Reference x
B.1. add B.2. copy B.3. delete B.4. edit B.5. export_design_file B.6. find_instances B.7. get_available_ips B.8. get_available_resource_types B.9. get_available_values B.10. get_first_error B.11. get_properties B.12. get_report B.13. get_report_names B.14. get_results B.15. get_value B.16. import_design_file B.17. move B.18. open_design_file B.19. pta::get_active_design B.20. pta::get_defaults B.21. pta::get_designs B.22. pta::locate B.23. pta::set_active_design B.24. pta::set_family B.25. recalculate_power B.26. redo B.27. save B.28. set_device B.29. set_view B.30. undo
1. Overview of the Power and Thermal Analyzer
2. Estimating Power Consumption with the Power and Thermal Analyzer
3. Power and Thermal Analyzer (PTA) Graphical User Interface
4. Power and Thermal Analyzer Resource Types
5. Command Line Options and Scripting
6. Factors Affecting the Accuracy of the Power and Thermal Analyzer
7. Document Revision History for the Power and Thermal Analyzer User Guide
A. Measuring Static Power
B. Tcl Command Reference

4.2. PTA - Root Entry

The Root Entry of the Power and Thermal Analyzer (PTA) displays thermal analysis options and allows you to enter device, package, and cooling information, as well as other device-wide settings such as HPS and default I/O and transceiver voltages.
Figure 30. PTA Root Entry

The required parameters depend on whether the junction temperature is manually entered or auto computed.

Note: Only parameters relevant to the currently selected device and settings are displayed.
Table 16.  Device Selection Parameters ( Agilex™ Devices)
Group Parameter Description
Transceiver Treatment of unused transceivers For Agilex™ FPGA portfolio device designs, specifies how unused transceivers, or used transceivers with unused channels, should be treated. The following options are available:
  • Power Down Unused Transceivers—the power rails of unused transceivers are set to 0V. Not applicable to devices with P-tile and E-tile.
  • Power Up Unused Transceivers—the power rails of unused transceivers are set to a non-zero voltage.
  • Preserve Unused Channels on Used and Unused Transceivers—the power rails of unused transceivers are set to a non-zero voltage and all unused PMA lanes on transceivers are preserved. Selecting Preserve Unused Channels on Used and Unused Transceivers results in the same behavior on the tiles as using the following global .qsf assignment: 
    set_global_assignment -name 
PRESERVE_UNUSED_XCVR_CHANNEL ON
Thermal TSD Mode Indicates the method by which sensor temperatures are reported. This parameter has no effect on maximum junction temperature or temperature margin.
Max Junction Temp, TJ-MAX (⁰C) Allows you to specify the maximum junction temperature that no part of any die in the package should exceed.
% Heat Through Top of Package Specify the portion of heat that passes through the top of the package.
Junction Temperature, TJ (⁰C) Specify the junction temperature for all dies in the package. This field is available when you select Use a constant junction temperature as the Calculation mode. In this mode, the junction temperatures for all dies in the package are assumed to have the specified value. To automatically compute junction temperatures, select one of the other options in the same field.
Cooling Solution ΨCA(⁰C/W) Allows you to specify the cooling solution when you have selected the Use a constant junction temperature, Find available thermal margin for cooling solution, or Find ambient temperature for specified cooling solution calculation mode.
Calculation Mode Specifies the calculation mode for the thermal solver to use. The available choices are:
  • Use a constant junction temperature.
  • Find cooling solution for maximum junction temperature limit.
  • Find available thermal margin for cooling solution.
  • Find ambient temperature for specified cooling solution.
Note: To enable selection of non-constant calculation modes, the Power characteristics field in the Device selection group box must be set to Maximum.
Apply Additional Margin Specifies, as a percentage, the amount of additional margin to apply to detailed thermal analysis results. The default value is 0%. Valid values are 0-25%. The recommended margin for Agilex 5 and Agilex™ 7 devices is 10%. Consult your Field Application Engineer (FAE) if you require additional guidance on margin power.
Ambient Temp, TA (⁰C) Allows you to specify the temperature of the air that is cooling the device.
Main Transceiver grade Select the required transceiver speed grade.
Power characteristics Select typical or maximum power. There is a process variation from die-to-die. This variation primarily affects static power consumption. If you choose Typical power characteristics, estimates are based on long term projections of average power consumed by typical silicon. For FPGA board power supply design and thermal design, choose Maximum for worst-case values.
Note: Typical power characteristics should not be used for regulator sizing or thermal analysis; use Maximum power characteristics for these activities.
Package Select the device package. Larger packages provide a larger cooling surface and more contact points to the circuit board; thus they offer lower thermal resistance. Package selection does not affect dynamic power directly.
Family Shows the device family selected at startup, either directly or through the imported file.
Device Grade Select the combination of Operating Temperature, Speed Grade, and Power Option used. Refer to the device datasheet for available combinations.
Device Select your device. Larger devices consume more static power and have higher clock dynamic power. All other power components are unaffected by device selection. The parameter and value table on the right side of the PTA root entry displays specifications of the currently selected device.
I/O Voltage setting for unused HVIO banks

Select a value to calculate voltage of unused HVIO banks.

This field applies only to Agilex 5 devices. Available values are 1.8V, 2.5V, 3.3V, and Power Down Unused GPIO Banks.
Voltage setting for unused GPIO banks Select a value to calculate voltage of unused GPIO banks. Available values are 1.0V, 1.05V, 1.1V, 1.2V, 1.3V, 1.5V, and Power Down Unused GPIO Banks.
Note: The availability of some voltage settings depend on the device selected.
HPS VCCL HPS Voltage (mV) Specifies the core HPS voltage (in mV).
Treatment of unused HPS cores Set whether unused HPS cores shall be powered up.
L3 Cache Size (MB) Size of the L3 Cache.
HPS System Switch Turns the HPS system on or off. This selection affects the static power.
Entity Name Specify an entity name in this column. This is an optional value.
CPU Freq. (MHz) Specifies the operating frequency of all CPUs (in MHz).
CPU Application Select a benchmark application representative of the application running on the CPUs.
A76 Cores Number of A76 CPU Cores.
A55 Cores Number of A55 CPU Cores.
A53 Cores Number of A53 CPU Cores.
Table 17.  Device Selection Parameters ( Stratix® 10 Devices)
Group Parameter Description
Main Device The currently selected device. Larger devices consume more static power and have higher clock dynamic power. All other power components are unaffected by device selection. The parameter and value table on the right side of the PTA root entry displays specifications of the currently selected device.
Power Characteristics

Select typical or maximum power. There is a process variation from die-to-die. This variation primarily affects static power consumption. If you choose Typical power characteristics, estimates are based on long term projections of average power consumed by typical silicon. For FPGA board power supply design and thermal design, choose Maximum for worst-case values.

Note: Typical power characteristics should not be used for regulator sizing or thermal analysis; use Maximum power characteristics for these activities.
Device Grade Select the combination of Operating Temperature, Speed Grade, and Power Option used. Refer to the device datasheet for available combinations.
Package Select the device package. Larger packages provide a larger cooling surface and more contact points to the circuit board; thus they offer lower thermal resistance. Package selection does not affect dynamic power directly.
Transceiver Grade Select the required transceiver speed grade.
VCC Voltage (mV) VCC Rail Voltage (where applicable).
Thermal Calculation Mode Specifies the calculation mode for the thermal solver to use. The available choices are these:
  • Use a constant junction temperature.
  • Find cooling solution for maximum junction temperature limit.
  • Find available thermal margin for cooling solution.
  • Find ambient temperature for specified cooling solution.
Note: To enable selection of non-constant calculation modes, the Power characteristics field in the Device selection group box must be set to Maximum.
TSD Mode Specify the method by which offset temperatures are provided—such as from a thermal diode, or a digital temperature sensing mechanism.
Cooling Solution ΨCA(°C/W) ψCA is the thermal resistance between the center of the package integrated heat spreader (IHS) and ambient temperature. The recommended ΨCA is the highest possible thermal resistance of the cooling solution that ensures no part of any die exceeds the specified maximum junction temperature.
Apply Additional Margin Specifies as a percentage, the amount of additional margin to apply to detailed thermal analysis results. The default value is 0%. Valid values are 0–25%. The recommended margin for Stratix 10 devices is 25%. Consult your Field Application Engineer (FAE) if you require additional guidance on margin power.
Note:
  1. Setting a non-zero margin causes the total power value on the Thermal page to be higher than the power reported elsewhere in the PTA.
  2. If you import a .ptc file from an earlier version of the PTC, which has the Apply Recommended Margin parameter set to Yes, the current version of the PTA interprets this as an Apply Additional Margin setting of 25%.
Junction temperature, TJ (°C) Specify the junction temperature for all dies in the package. This field applies only when the selected Calculation mode value is Use a constant junction temperature.
Max. Junction Temp, TJ-MAX (°C) Specify the maximum junction temperature that no part of any die in the package should exceed.
Ambient Temp, TA (°C) Specify the temperature of the air that is cooling the device.
HPS HPS System Switch Turns the HPS system on or off. This selection affects the static power.
CPU Application Select a benchmark application representative of the application running on the CPUs.
VCCL_HPS Voltage (mV) Specifies the core HPS voltage (in mV).
Entity Name Specifies a name for the entity. This is an optional value.
CPU Freq. (MHz) Specifies the operating frequency of all CPUs (in MHz).
Number of CPU Cores Specifies the number of cores in the CPU running the selected application.
Transceiver Treatment of unused transceiver dies

For Stratix® 10 devices, if you use no transceiver channels or PLLs on an HSSI die, you can power down the die or the die can remain powered. You can select the voltage of unused dies that are powered to minimize static power, or to minimize the number of power supply voltages required.

For example, if active H-tile transceiver channels use VCCR_GXB=1.12V, selecting Minimize Leakage assumes that the unused-but-powered H-tile dies use VCCR_GXB=1.03V, which is the lowest supported voltage, thus minimizing leakage.

Selecting Minimize Number of Supply Voltages assumes that the unused-but-powered banks use VCCR_GXB=1.12V, which is the voltage used by active channels, thus eliminating the need for the 1.03V power supply on VCCR_GXB.

The PTA uses information in the XCVR Die ID, Starting Channel Location, and # of Channels properties on Transceiver resource entries, along with the # PLL Blocks and XCVR Die ID properties on PLL resource entries to determine whether dies are actively used. This setting does not apply to E-tile nor P-tile transceivers, because these transceiver dies can never be powered down.
Note: Only parameters relevant to the currently selected device and settings are displayed.

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