Power and Thermal Analyzer User Guide

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ID 865226
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Power and Thermal Analyzer 2. Estimating Power Consumption with the Power and Thermal Analyzer 3. Power and Thermal Analyzer (PTA) Graphical User Interface 4. Power and Thermal Analyzer Resource Types 5. Command Line Options and Scripting 6. Factors Affecting the Accuracy of the Power and Thermal Analyzer 7. Document Revision History for the Power and Thermal Analyzer User Guide A. Measuring Static Power B. Tcl Command Reference
1. Overview of the Power and Thermal Analyzer x
1.1. Accessing the Power and Thermal Analyzer 1.2. PTA Power Model Status 1.3. Definitions of Power Terms Used in this Document
2. Estimating Power Consumption with the Power and Thermal Analyzer x
2.1. Estimating Power Before Starting the FPGA Design 2.2. Estimating Power While Creating the FPGA Design 2.3. Estimating Power After Completing the FPGA Design 2.4. Estimating Power for Dual-Core Devices
3. Power and Thermal Analyzer (PTA) Graphical User Interface x
3.1. PTA - Device Selector Dialog Box 3.2. PTA - Primary GUI Components 3.3. PTA - Hierarchical Design Editor 3.4. PTA - Using Design Hierarchies in the Power and Thermal Analyzer 3.5. PTA - Entering Hierarchy Information Into the PTA 3.6. PTA - Current Drawn per Supply Tab 3.7. PTA - Temperature and Cooling Tab 3.8. PTA - Resource Utilization Panel 3.9. PTA - Register Dynamic Power in Agilex Devices 3.10. PTA - Input Fields 3.11. PTA - Data Entry Error Messages 3.12. PTA - Search Features 3.13. PTA - Filtered Searches 3.14. PTA - Using the Tcl Console to Perform Searches
4. Power and Thermal Analyzer Resource Types x
4.1. PTA - Power Summary 4.2. PTA - Root Entry 4.3. PTA - Instance 4.4. PTA - Logic Resource Type 4.5. PTA - RAM Resource Type 4.6. PTA - DSP Resource Type 4.7. PTA - Clock Resource Type 4.8. PTA - PLL Resource Type 4.9. PTA - I/O Resource Type 4.10. PTA - Transceiver Resource Type 4.11. PTA - Crypto Resource Type 4.12. PTA - NOC Resource Type 4.13. PTA - HBM Resource Type
4.10. PTA - Transceiver Resource Type x
4.10.1. PTA - Estimating E-Tile Channel PLL Power
5. Command Line Options and Scripting x
5.1. Invoking the Power and Thermal Analyzer from the Command Line 5.2. Running Scripts with the Power and Thermal Analyzer
6. Factors Affecting the Accuracy of the Power and Thermal Analyzer x
6.1. Toggle Rate 6.2. I/O Bank Allocation
B. Tcl Command Reference x
B.1. add B.2. copy B.3. delete B.4. edit B.5. export_design_file B.6. find_instances B.7. get_available_ips B.8. get_available_resource_types B.9. get_available_values B.10. get_first_error B.11. get_properties B.12. get_report B.13. get_report_names B.14. get_results B.15. get_value B.16. import_design_file B.17. move B.18. open_design_file B.19. pta::get_active_design B.20. pta::get_defaults B.21. pta::get_designs B.22. pta::locate B.23. pta::set_active_design B.24. pta::set_family B.25. recalculate_power B.26. redo B.27. save B.28. set_device B.29. set_view B.30. undo
1. Overview of the Power and Thermal Analyzer
2. Estimating Power Consumption with the Power and Thermal Analyzer
3. Power and Thermal Analyzer (PTA) Graphical User Interface
4. Power and Thermal Analyzer Resource Types
5. Command Line Options and Scripting
6. Factors Affecting the Accuracy of the Power and Thermal Analyzer
7. Document Revision History for the Power and Thermal Analyzer User Guide
A. Measuring Static Power
B. Tcl Command Reference

4.10.1. PTA - Estimating E-Tile Channel PLL Power

You can estimate E-tile channel PLL power for Stratix® 10 devices, by adding a Transmitter-only Transceiver resource.

The following three examples illustrate the PTA configuration for various E-tile channel PLL requirements.

Table 27.  E-Tile Channel PLL configured for: Reference clock = 200MHz, pll_clkout1 = 800MHz, pll_clkout2 = 400MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter only 12800 16 Normal power Bypass Bypass NRZ 0 1 200 0

Table 28.  E-Tile Channel PLL configured for: Reference clock = 125MHz, pll_clkout1 = 500MHz, pll_clkout2 = 250MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter only 8000 16 Normal power Bypass Bypass NRZ 0 1 125 0

Table 29.  E-Tile Channel PLL configured for: Reference clock = 307MHz, pll_clkout1 = 491MHz, pll_clkout2 = 245MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter only 19660.8 40 Normal power Bypass Bypass NRZ 0 1 307 0

Alternatively, you can instantiate an E-Tile Transceiver-native PHY IP in PLL mode in your Quartus® Prime project, compile the project, and view the configuration in the PTA.

Level Two Title