FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

8.2.1. [OFS-PCIE] Setup the OFS Environment for the FPGA Device

Before you can program the FPGA device with the OFS for PCIe* attach design example, you must set up the FPGA device with the OFS framework components and ensure that the OPAE drivers on the host system run correctly.

These steps must be done whenever the system hosting the FPGA board is power-cycled or soft-rebooted.

To set up the FPGA device:
  1. Ensure that the PCIe bifurcation BIOS setting on the host machine that hosts the FPGA card is set as follows, depending on the target board:
    • Agilex™ 7 FPGA I-Series Development Kit: x8
    • Intel® FPGA SmartNIC N6001-PL Platform: Auto
  2. Program the FPGA devices with the .sof file for the OFS 2024.3 slim FIM for your board:
    Program the FPGA with the following command:
    quartus_pgm -c 1 -m jtag \
                -o "p;<path to the sof file>/ofs_top.sof@1"
  3. Soft-reboot the machine with the following command:
    sudo reboot

    A soft reboot is required whenever you program the FPGA with a .sof file (SRAM object file) so that the PCIe* host can reenumerate the attached devices. A hard reboot or power cycle would require you to reprogram the FPGA device with the earlier command.

  4. If you want to use a non-root user to run inference on the FPGA board, complete the following steps:
    1. Set user process resource limits as follows:
      1. Create a rule file at /etc/security/limits.d/90-intel-fpga-ofs-limits.conf with the following content:
        soft memlock unlimited
        
        hard memlock unlimited
      2. Log out of your current session and log back in.
      3. Run the ulimit -l command to ensure that limits are set to unlimited.
    2. Enable huge pages help improve the performance of DMA operations between host and FPGA device. Enable huge pages as follows:
      1. Create a rule file at /etc/sysctl.d/intel-fpga-ofs-sysctl.conf with the following content:
        vm.nr_hugepages = 2048
      2. Create a rule file at /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages with the following content:
        2048
    3. Set the permissions for the OFS device feature list (DFL) framework as follows:
      1. Create a rule file at /etc/udev/rules.d named 90-intel-fpga-ofs.rules with the following content:
        KERNEL=="dfl-fme.[0-9]", ACTION=="add|change", GROUP="root", MODE="0666", RUN+="/bin/bash -c 'chmod 0666 %S%p/errors/ /dev/%k'"
        
        KERNEL=="dfl-port.[0-9]", ACTION=="add|change", GROUP="root", MODE="0666", RUN+="/bin/bash -c 'chmod 0666 %S%p/dfl/userclk/frequency %S%p/errors/* /dev/%k'"
        
        Ensure you enter the content as two lines only. The lines are line-wrapped only due to document formatting restrictions.
      2. Run the following commands:
        sudo udevadm control --reload
        
        sudo udevadm trigger /dev/dfl-fme.0
        
        sudo udevadm trigger /dev/dfl-port.0
        
    4. Set the permissions for userspace I/O (UIO) devices as follows:
      1. Create a rule file at /etc/udev/rules.d named uio.rules with the following content:
        SUBSYSTEM=="uio" KERNEL=="uio*" MODE="0666"
      2. Run the following commands:
        sudo udevadm control --reload
        
        sudo udevadm trigger --subsystem-match=uio --settle
        
    5. Initialize the OPAE SDK.

      You must initialize the OPAE SDK after every system power cycle or soft reboot. You can make this initialization persistent by using a systemd startup service.

      To initialize the OPAE SDK:
      1. Determine the PCIe* B:d.F (system, bus, device, function) of your board by running the fpgainfo command:
        sudo fpgainfo fme
        In the output, look for a line similar to the following line:
        PCIe s:b:d.f                     : 0000:03:00.0
      2. (For Agilex™ 7 FPGA I-Series Development Kit only) Assign the first SR-IOF virtual function to the FPGA board with the following command:
        sudo pci_device s:b:d.f vf 1
      3. Initialize opae.io with the following command:
        sudo opae.io init -d s:b:d.1 <your user name>
        Note: The original function (f in s:b:d.f) value that the fpgainfo command reported is replaced here by 1.
  5. Ensure that the OPAE_PLATFORM_ROOT environment variable points to your OFS FPGA interface manager (FIM) pr_build_template directory.