1. FPGA AI Suite Design Examples User Guide
2. FPGA AI Suite Design Examples
3. Design Example Components
4. [PCIE] Getting Started with the FPGA AI Suite PCIe* -based Design Example
5. [PCIE] Building the FPGA AI Suite Runtime
6. [PCIE] Running the Design Example Demonstration Applications
7. [PCIE] Design Example System Architecture for the Agilex™ 7 FPGA
8. [OFS-PCIE] Getting Started with Open FPGA Stack (OFS) for PCIe* -Attach Design Examples
9. [OFS-PCIE] Design Example Components
10. [HL-NO-DDR] Getting Started with the FPGA AI Suite DDR-Free Design Example
11. [HL-NO-DDR] Running the Hostless DDR-Free Design Example
12. [HL-NO-DDR] Design Example System Architecture
13. [HL-NO-DDR] Quartus® Prime System Console
14. [HL-NO-DDR] JTAG to Avalon MM Host Register Map
15. [HL-NO-DDR] Updating MIF Files
16. [HL-JTAG] Getting Started
17. [HL-JTAG] Design Example Components
18. [SOC] FPGA AI Suite SoC Design Example Prerequisites
19. [SOC] FPGA AI Suite SoC Design Example Quick Start Tutorial
20. [SOC] FPGA AI Suite SoC Design Example Run Process
21. [SOC] FPGA AI Suite SoC Design Example Build Process
22. [SOC] FPGA AI Suite SoC Design Example Quartus® Prime System Architecture
23. [SOC] FPGA AI Suite SoC Design Example Software Components
24. [SOC] Streaming-to-Memory (S2M) Streaming Demonstration
A. FPGA AI Suite Example Designs User Guide Archives
B. FPGA AI Suite Example Designs User Guide Revision History
6.1. [PCIE] Exporting Trained Graphs from Source Frameworks
6.2. [PCIE] Compiling Exported Graphs Through the FPGA AI Suite
6.3. [PCIE] Compiling the PCIe* -based Example Design
6.4. [PCIE] Programming the FPGA Device ( Agilex™ 7)
6.5. [PCIE] Performing Accelerated Inference with the dla_benchmark Application
6.6. [PCIE] Running the Ported OpenVINO™ Demonstration Applications
8.2.1. [OFS-PCIE] Setup the OFS Environment for the FPGA Device
8.2.2. [OFS-PCIE] Exporting Trained Graphs from Source Frameworks.
8.2.3. [OFS-PCIE] Compiling Exported Graphs Through the FPGA AI Suite
8.2.4. [OFS-PCIE] Compiling the OFS for PCIe* Attach Design Example
8.2.5. [OFS-PCIE] Programming the FPGA Green Bitstream
8.2.6. [OFS-PCIE] Performing Accelerated Inference with the dla_benchmark application
16.1. [HL-JTAG] Prerequisites
16.2. [HL-JTAG] Building the FPGA AI Suite Runtime
16.3. [HL-JTAG] Building an FPGA Bitstream for the JTAG Design Examples
16.4. [HL-JTAG] Programming the FPGA Device
16.5. [HL-JTAG] Preparing Graphs for Inference with FPGA AI Suite
16.6. [HL-JTAG] Performing Inference on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit
16.7. [HL-JTAG] Inference Performance Measurement
16.8. [HL-JTAG] Known Issues and Limitations
19.1. [SOC] Initial Setup
19.2. [SOC] Initializing a Work Directory
19.3. [SOC] (Optional) Create an SD Card Image (.wic)
19.4. [SOC] Writing the SD Card Image (.wic) to an SD Card
19.5. [SOC] Preparing SoC FPGA Development Kits for the FPGA AI Suite SoC Design Example
19.6. [SOC] Adding Compiled Graphs (AOT files) to the SD Card
19.7. [SOC] Verifying FPGA Device Drivers
19.8. [SOC] Running the Demonstration Applications
19.5.1. [SOC] Preparing the Agilex™ 5 FPGA E-Series 065B Modular Development Kit
19.5.2. [SOC] Preparing the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit
19.5.3. [SOC] Preparing the Arria® 10 SX SoC FPGA Development Kit
19.5.4. [SOC] Configuring the SoC FPGA Development Kit UART Connection
19.5.5. [SOC] Determining the SoC FPGA Development Kit IP Address
19.5.1.1. [SOC] Confirming the Agilex™ 5 FPGA E-Series 065B Modular Development Kit Board Setup
19.5.1.2. [SOC] Programming the Agilex™ 5 FPGA Device with the JTAG Indirect Configuration (.jic) File
19.5.1.3. [SOC] Programming the Agilex™ 5 FPGA Device with the SRAM Object File (.sof)
19.5.1.4. [SOC] Connecting the Agilex™ 5 FPGA E-Series 065B Modular Development Kit to the Host Development System
19.5.2.1. [SOC] Confirming Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit Board Set Up
19.5.2.2. [SOC] Programming the Agilex™ 7 FPGA Device with the JTAG Indirect Configuration (.jic) File
19.5.2.3. [SOC] Programming the Agilex™ 7 FPGA Device with the SRAM Object File (.sof)
19.5.2.4. [SOC] Connecting the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit to the Host Development System
22.1. [SOC] FPGA AI Suite SoC Design Example Inference Sequence Overview
22.2. [SOC] Memory-to-Memory (M2M) Variant Design
22.3. [SOC] Streaming-to-Memory (S2M) Variant Design
22.4. [SOC] Top Level
22.5. [SOC] The SoC Design Example Platform Designer System
22.6. [SOC] Fabric EMIF Design Component
22.7. [SOC] PLL Configuration
23.1.1. [SOC] Yocto Recipe: recipes-core/images/coredla-image.bb
23.1.2. [SOC] Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbappend
23.1.3. [SOC] Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
23.1.4. [SOC] Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
23.1.5. [SOC] Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_%.bbappend
23.1.6. [SOC] Yocto Recipe: recipes-support/devmem2/devmem2_2.0.bb
23.1.7. [SOC] Yocto Recipe: wic
8.2.1. [OFS-PCIE] Setup the OFS Environment for the FPGA Device
Before you can program the FPGA device with the OFS for PCIe* attach design example, you must set up the FPGA device with the OFS framework components and ensure that the OPAE drivers on the host system run correctly.
These steps must be done whenever the system hosting the FPGA board is power-cycled or soft-rebooted.
To set up the FPGA device:
- Ensure that the PCIe bifurcation BIOS setting on the host machine that hosts the FPGA card is set as follows, depending on the target board:
- Agilex™ 7 FPGA I-Series Development Kit: x8
- Intel® FPGA SmartNIC N6001-PL Platform: Auto
- Program the FPGA devices with the .sof file for the OFS 2024.3 slim FIM for your board:
- Agilex™ 7 FPGA I-Series Development Kit: https://github.com/OFS/ofs-agx7-pcie-attach/releases/download/ofs-2024.3/iseries-dk-slimfim-images_ofs-2024-3-0.tar.gz
- Intel® FPGA SmartNIC N6001-PL Platform: https://github.com/OFS/ofs-agx7-pcie-attach/releases/download/ofs-2024.3/n6001-slimfim-images_ofs-2024-3-0.tar.gz
Program the FPGA with the following command:quartus_pgm -c 1 -m jtag \ -o "p;<path to the sof file>/ofs_top.sof@1"
- Soft-reboot the machine with the following command:
sudo reboot
A soft reboot is required whenever you program the FPGA with a .sof file (SRAM object file) so that the PCIe* host can reenumerate the attached devices. A hard reboot or power cycle would require you to reprogram the FPGA device with the earlier command.
- If you want to use a non-root user to run inference on the FPGA board, complete the following steps:
- Set user process resource limits as follows:
- Create a rule file at /etc/security/limits.d/90-intel-fpga-ofs-limits.conf with the following content:
soft memlock unlimited hard memlock unlimited
- Log out of your current session and log back in.
- Run the ulimit -l command to ensure that limits are set to unlimited.
- Create a rule file at /etc/security/limits.d/90-intel-fpga-ofs-limits.conf with the following content:
- Enable huge pages help improve the performance of DMA operations between host and FPGA device. Enable huge pages as follows:
- Create a rule file at /etc/sysctl.d/intel-fpga-ofs-sysctl.conf with the following content:
vm.nr_hugepages = 2048
- Create a rule file at /sys/kernel/mm/hugepages/hugepages-2048kB/nr_hugepages with the following content:
2048
- Create a rule file at /etc/sysctl.d/intel-fpga-ofs-sysctl.conf with the following content:
- Set the permissions for the OFS device feature list (DFL) framework as follows:
- Create a rule file at /etc/udev/rules.d named 90-intel-fpga-ofs.rules with the following content:
KERNEL=="dfl-fme.[0-9]", ACTION=="add|change", GROUP="root", MODE="0666", RUN+="/bin/bash -c 'chmod 0666 %S%p/errors/ /dev/%k'" KERNEL=="dfl-port.[0-9]", ACTION=="add|change", GROUP="root", MODE="0666", RUN+="/bin/bash -c 'chmod 0666 %S%p/dfl/userclk/frequency %S%p/errors/* /dev/%k'"
Ensure you enter the content as two lines only. The lines are line-wrapped only due to document formatting restrictions. - Run the following commands:
sudo udevadm control --reload sudo udevadm trigger /dev/dfl-fme.0 sudo udevadm trigger /dev/dfl-port.0
- Create a rule file at /etc/udev/rules.d named 90-intel-fpga-ofs.rules with the following content:
- Set the permissions for userspace I/O (UIO) devices as follows:
- Create a rule file at /etc/udev/rules.d named uio.rules with the following content:
SUBSYSTEM=="uio" KERNEL=="uio*" MODE="0666"
- Run the following commands:
sudo udevadm control --reload sudo udevadm trigger --subsystem-match=uio --settle
- Create a rule file at /etc/udev/rules.d named uio.rules with the following content:
- Initialize the OPAE SDK.
You must initialize the OPAE SDK after every system power cycle or soft reboot. You can make this initialization persistent by using a systemd startup service.
To initialize the OPAE SDK:- Determine the PCIe* B:d.F (system, bus, device, function) of your board by running the fpgainfo command:
sudo fpgainfo fme
In the output, look for a line similar to the following line:PCIe s:b:d.f : 0000:03:00.0
- (For Agilex™ 7 FPGA I-Series Development Kit only) Assign the first SR-IOF virtual function to the FPGA board with the following command:
sudo pci_device s:b:d.f vf 1
- Initialize opae.io with the following command:
sudo opae.io init -d s:b:d.1 <your user name>
Note: The original function (f in s:b:d.f) value that the fpgainfo command reported is replaced here by 1.
- Determine the PCIe* B:d.F (system, bus, device, function) of your board by running the fpgainfo command:
- Set user process resource limits as follows:
- Ensure that the OPAE_PLATFORM_ROOT environment variable points to your OFS FPGA interface manager (FIM) pr_build_template directory.