16.6. [HL-JTAG] Performing Inference on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit
After the FPGA device on the Agilex™ 5 FPGA E-Series 065B Modular Development Kit has been programmed, you can perform inference.
- Bitstream file location
The default bitstream path is top.sof located in the $COREDLA_WORK directory.
You can override this default location by specifying the DLA_SOF_PATH environment variable.
- Quartus® Prime System Console Tcl script (required to properly claim JTAG services)
The default script is $COREDLA_WORK/runtime/build_Release/system_console_script.tcl.
You can override this value by specifying the DLA_SYSCON_SOURCE_FILE environment variable.
# Modify MODEL to suit your application export DLA_SOF_PATH=$COREDLA_WORK/build_agx5_jtag_ed/AGX5_Generic.sof export MODEL=<path-to-model-XML-file>/resnet50.xml cd $COREDLA_WORK/runtime/build_Release/dla_benchmark dla_benchmark \ -b=1 \ -m=$MODEL \ -d=HETERO:FPGA,CPU \ -i <path-to-image-files> \ -niter=2 \ -plugins=../../plugins.xml \ -arch_file= $COREDLA_ROOT/example_architectures/AGX5_Generic.arch \ -api=async \ -perf_est \ -nireq=1 -dump_output -report_lsu_counters -enable_early_access
By default, the dla_benchmark application records the system-console commands that are executed during inference in a log file named csr_log.txt in the current work directory, and preserves the intermediate files created during inference. To prevent the creation of the log file and intermediate files, specify the -dump_csr=false of the dla_benchmark command.
For more information about the dla_benchmark application, refer to [PCIE] Performing Accelerated Inference with the dla_benchmark Application.