FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

3.3.7.2. Agilex™ 7 PCIe-Attach OFS-based BSP Example

For OFS-based devices, the BSP consists of a platform-specific FPGA interface manager (FIM) and a platform-agnostic accelerator functional unit (AFU).

The FPGA AI Suite OFS for PCIe* attach design example supports Agilex™ 7 PCIe* Attach OFS.

You can obtain the source files needed to build a Agilex™ 7 PCIe* Attach FIM or obtain prebuillt FIMs for some boards from OFS Agilex 7 PCIe Attach FPGA Development Directory in GitHub.

The AFU wraps the FPGA AI Suite IP and must meet the following general requirements:

  • The AFU must include an instance of the FPGA AI Suite IP.
  • The AFU must support host access (for example, via DMA) to external memory that is shared with the FPGA AI Suite IP.
  • The AFU must propagate interrupts from the FPGA AI Suite IP to the host.
  • The AFU Must support host access to the FPGA AI Suite IP CSR memory.
If you are creating your own FPGA AI Suite AFU, consider starting with an AFU example design that implements some of the required functionality. Some examples designs and what they are offer are as follows:
  • For an example of enabling direct memory access so the host can access DDR memory, review the direct memory access (DMA) AFU example on GitHub
  • For an example of interrupt handling, review the oneAPI Accelerator Support Package (ASP) on GitHub.
  • For an example MMD implementation, review the oneAPI Accelerator Support Package (ASP) on GitHub.