FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

17.1. [HL-JTAG] Hardware Components

The FPGA AI Suite JTAG design example uses a JTAG-USB connection on the development kit to facilitate host-FPGA transactions. The following diagram shows a simplified block diagram of the design.

Figure 12. Simplified System Design of the JTAG Design Example

The design example stores filter weights, biases, configurations for the FPGA AI Suite IP, graph inputs, outputs, and intermediate data on the lower 2GB of a DDR4 memory interface, similar to the PCIe-based design examples. An external memory interface (EMIF) IP manages the DDR4 memory and toggles the 32-bit interface at 1600 MT/s.

The FPGA AI Suite IP can typically meet timing at around 300 MHz and accesses the EMIF IP via a 128-bit AXI4 data interface clocked at 200 MHz. The IP can only access the first 2GB of the memory.

The host uses a JTAG-Avalon Bridge IP to access the DDR4 memory, as well as the CSR registers of the FPGA AI Suite IP via a 32-bit Avalon-MM interface clocked at 100 MHz. As seen from the JTAG-Avalon Bridge IP, the subordinates reside at the addresses outlined in the following table:
Table 11.  Subordinate Addresses Accessible from the JTAG-Avalon Interface
External Memory FPGA AI Suite IP CSRs
Address Range (Bytes) 0x0000_0000 – 0x7FFF_FFFF 0x8000_0000 – 0x8000_0FFF

To investigate and modify the implementation of the hardware components, review the source files of the system design part of the design example in the $COREDLA_ROOT/platform/a5e_modular_devkit_jtag directory.