FPGA AI Suite: Design Examples User Guide

ID 848957
Date 4/30/2025
Public
Document Table of Contents

22.4.1. [SOC] Clock Domains

There are three main clocks within this design. All the clocks are considered asynchronous to each other. The SDC file provided has the clocking constraints for this design.

The design clocks are as follows:
Table 18.  SDC Clock Domains for SoC Design Example
Clock Clock Description Agilex™ 5 Design Clock Frequency Agilex™ 7 Design Clock Frequency Arria® 10 Design Clock Frequency
Board clock This clock is used for all mSGDMA infrastructure and CPU CSR interfaces. The HPS AXI interfaces all run off this clock. 100 MHz 100 MHz 100 MHz
DLA clock This clock is used only by the FPGA AI Suite IP. It feeds the dla_clk pin and is used inside FPGA AI Suite IP PE array. 200 MHz 400 MHz 200 MHz
DDR clock This is used for the DDR controller and interconnect between the DLA and DDR. This interface is used by the DLA to transfer workloads back and forth to system memory. 200 MHz 333 MHz 266 MHz