3.1.3. Building FPGA AI Suite Design Examples
To build FPGA AI Suite design examples, specify the build option of the design example utility.
dla_build_example_design.py build \ <design_example_identifier> \ <architecture file>
dla_build_example_design.py build \ agx7_de10_pcie \ $COREDLA_ROOT/example_architectures/AGX7_Generic.arch
dla_build_example_design.py build \ --output-dir <directory> \ <design_example_identifier> \ <architecture file>
Be default, the utility also prevents the build directory from being overwritten. You can override this behavior with the --force option.
After the build is complete, the build directory has the following files and folders:
- coredla_ip/
This folder contains the RTL for the configured FPGA AI Suite IP.
- hw/
This folder contains the Quartus® Prime or Open FPGA Stack (OFS) project files. It also includes its own self-contained copy of the contents of the coredla_ip/ folder
- .build.json
This contents of this file (sometimes referred to as the "build context" file) allow the build to be split into multiple steps.
- Reports
The build directory will contain any log files generated by the build utility (such as build.log) and the QoR summary that is generated by a successful compilation.
- Bitstreams
This build directory will contain the bitstreams to program the target FPGA device as follows:
- For OFS-based designs, .gbs files.
- For other designs, .sof and.rbf files.