GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
1.4. Agilex® 3 Ethernet Portfolio and Target Applications
Agilex® 3 devices serve a broad range of applications that require high performance, lower power, smaller form factors and lower logic densities.
These characteristics make Agilex® 3 ideal for midrange FPGA applications across the edge and core including:
- Wireless and wireline communications
- Video and broadcast equipment
- Industrial applications
- Test and measurement products
- Medical electronics
- Data center
- Defense applications
The majority of the applications listed above require Ethernet connectivity. Intel provides Ethernet IPs that support these applications.
The following table lists the Agilex® 3 Ethernet IP Portfolio supported in Quartus® Prime Pro Edition software version 25.1. This user guide focuses on the GTS Ethernet Hard IP and its example designs.
IP | Description |
---|---|
GTS Ethernet Hard IP | GTS Ethernet Hard IP includes a configurable, hardened blocks MAC, PCS, and PMA, as well as optional FEC for Ethernet applications. It supports the following:
|
1G/2.5G/5G/10G Multi-rate Ethernet PHY IP | Includes a Physical Coding Sublayer (PCS) and Physical Media Attachment (PMA). You can dynamically switch the PHY operating speed. The IP uses the GTS Transceiver for serial transmission, with soft logic added to connect the MAC interface. |
Low Latency Ethernet 10G MAC IP | To build a complete Ethernet subsystem in an Intel FPGA device and connect it to an external device, combine the Low Latency Ethernet 10G MAC IP with an Intel FPGA PHY IP or any of the supported PHYs. |
Triple-Speed Ethernet for Intel® FPGA IP | Incorporates a 10/100/1000 Mbps Ethernet Media Access Controller (MAC) as well as an optional 1000 BASE-X/SGMII Physical Coding Sublayer (PCS) with Physical Medium Attachment (PMA) built with on-chip transceiver I/Os or LVDS I/Os. |