GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
6.3.2. Simulators Output
The following sample output illustrates a successful simulation test run of the MII PCS only in VCS* MX simulator. The script and waveform output is similar for other supported simulators.
# rck0_per = 6400.000000 # # ---TX reset sequence completed ----- # The time now is 30000000000 # # ---RX reset sequence completed ----- # The time now is 40000000000 # # ---IP_INST[0] Test 0; ---Total 16 packets to send----- # ------IP_INST[0] Start pkt gen TX----- # ------Checking Packet TX/RX result----- ------------ 1 packets Sent; 0 packets Received-------- ------------ 3 packets Sent; 0 packets Received-------- ------------ 6 packets Sent; 3 packets Received-------- ------------ 9 packets Sent; 6 packets Received-------- The time now is 50000000000 ------------ 9 packets Sent; 7 packets Received-------- ------------ 9 packets Sent; 7 packets Received-------- ------------ 16 packets Sent; 14 packets Received-------- ------ALL 16 packets Sent out--- ------------ 16 packets Sent; 16 packets Received-------- ------ALL 16 packets Received--- ------TX/RX packet check OK--- ****Starting AVMM Read/Write**** ====>MATCH! Read addr = 00000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 ====>MATCH! Read addr = 00000108, ReaddataValid = 1 Readdata = 00000007 Expected_Readdata = 00000007 ====>MATCH! Read addr = 00100004, ReaddataValid = 1 Readdata = 12153524 Expected_Readdata = 12153524 ====>MATCH! Read addr = 00100008, ReaddataValid = 1 Readdata = c0895e81 Expected_Readdata = c0895e81 ====>MATCH! Read addr = 00000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 ====>MATCH! Read addr = 00060008, ReaddataValid = 1 Readdata = 000000ff Expected_Readdata = 000000ff ====>MATCH! Read addr = 000a5000, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 **** AVMM Read/Write Operation Completed for IP_INST[ 0]**** ** Testbench complete ** *****************************************
The following sample waveform illustrates a simulation test run for MII PCS only VCS* MX simulator.