GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

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ID 848477
Date 7/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Install and License the GTS Ethernet Hard IP 3. Configure and Generate Ethernet Hard IP variant 4. Integrate GTS Ethernet Hard IP into Your Application 5. Simulate and Compile (MAC+PCS) Design Example 6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example 7. Simulate and Compile SyncE Design Example 8. Simulate and Compile PTP1588 Design Example 9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode) 10. Simulate and Compile - Auto-Negotiation and Link Training 11. Troubleshoot and Diagnose Issues 12. Appendix A: Functional Description 13. Appendix B: Configuration Registers 14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
1. Overview x
1.1. Release Information 1.2. High-Level Functional Overview 1.3. Acronyms 1.4. Agilex® 3 Ethernet Portfolio and Target Applications 1.5. Agilex® 3 Ethernet Hard IP Features 1.6. GTS Ethernet Hard IP Design Flow
1.5. Agilex® 3 Ethernet Hard IP Features x
1.5.1. Device Family Support 1.5.2. Device Speed Grade Support 1.5.3. Resource Utilization 1.5.4. Round-Trip Latency
3. Configure and Generate Ethernet Hard IP variant x
3.1. Create Quartus Project 3.2. Configure GTS Ethernet Hard IP 3.3. Generate HDL for Synthesis and Simulation 3.4. Generated File Structure 3.5. Generate GTS EHIP Design Example 3.6. Analog Parameter Options
3.5. Generate GTS EHIP Design Example x
3.5.1. Directory Structure
4. Integrate GTS Ethernet Hard IP into Your Application x
4.1. Implement Required Clocking 4.2. Implement Required Resets 4.3. Connect the Status Interface 4.4. Connect the MAC Avalon Streaming Client Interface 4.5. Connect the MII PCS Only Client Interface 4.6. Connect the PCS66 Client Interface – FlexE and OTN 4.7. Connect the Precision Time Protocol Interface 4.8. Connect the Ethernet Hard IP Reconfiguration Interface 4.9. Connect the Auto-Negotiation and Link Training 4.10. Connect the Multirate Auto-Negotiation and Link Training 4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.1. Implement Required Clocking x
4.1.1. Implement MAC Synchronous Clock Connections 4.1.2. Implement Clock Connections to MAC Asynchronous Operation 4.1.3. Implement Clock Connections in Synchronous Ethernet Operation (Sync-E) 4.1.4. Implement Clock Connections in PTP-Based Design
4.2. Implement Required Resets x
4.2.1. Reset Sequence 4.2.2. Connect the GTS Reset Sequencer IP
4.2.2. Connect the GTS Reset Sequencer IP x
4.2.2.1. Requirements and Considerations for GTS Reset Sequencer IP
4.3. Connect the Status Interface x
4.3.1. Use i_stats_snapshot to Read Stats Counters
4.4. Connect the MAC Avalon Streaming Client Interface x
4.4.1. Connect the TX MAC Avalon Streaming Client Interface 4.4.2. Connect the RX MAC Avalon Streaming Client Interface 4.4.3. Connect the MAC Flow Control Interface
4.4.1. Connect the TX MAC Avalon Streaming Client Interface x
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough 4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough 4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion 4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2. Connect the RX MAC Avalon Streaming Client Interface x
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled 4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled 4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled 4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
4.4.3. Connect the MAC Flow Control Interface x
4.4.3.1. Connect the TX MAC Flow Control Interface 4.4.3.2. Connect the RX MAC Flow Control Interface
4.5. Connect the MII PCS Only Client Interface x
4.5.1. Connect the MII PCS Mode TX Interface 4.5.2. Connect the MII PCS Mode RX Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN x
4.6.1. Connect the FlexE and OTN Mode TX Interface 4.6.2. Connect the FlexE and OTN Mode RX Interface
4.7. Connect the Precision Time Protocol Interface x
4.7.1. Connect the Time-of-Day Interface 4.7.2. Connect the TX Two-Step Timestamp Interface 4.7.3. Connect the TX One-Step Timestamp Interface 4.7.4. Connect the RX Timestamp Interface 4.7.5. Connect the PTP Status Interface
4.7.3. Connect the TX One-Step Timestamp Interface x
4.7.3.1. PTP Field Offset for 1-Step Operation
5. Simulate and Compile (MAC+PCS) Design Example x
5.1. Design Example Features 5.2. Design Example Components 5.3. Simulate the Design Example 5.4. Compile the Design Example
5.3. Simulate the Design Example x
5.3.1. Simulation Testbench Flow 5.3.2. Verify the Simulation Results
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example x
6.1. Design Example Features 6.2. Design Example Components 6.3. Simulate the Design Example 6.4. Compile the Design Example
6.3. Simulate the Design Example x
6.3.1. Simulation Testbench Flow 6.3.2. Simulators Output
7. Simulate and Compile SyncE Design Example x
7.1. Design Example Features 7.2. Design Example Components 7.3. Simulate the Design Example 7.4. Compile the Design Example
7.3. Simulate the Design Example x
7.3.1. Simulation Testbench Flow 10GE Ethernet with SyncE 7.3.2. Simulator Output
8. Simulate and Compile PTP1588 Design Example x
8.1. Design Example Features 8.2. Design Example Components 8.3. Simulate the Design Example 8.4. Compile the Design Example
8.3. Simulate the Design Example x
8.3.1. Simulation Testbench Flow 8.3.2. Simulator Output
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode) x
9.1. Design Example Features 9.2. Design Example Components 9.3. Simulate the Design Example 9.4. Compile the Design Example
9.3. Simulate the Design Example x
9.3.1. Simulation Testbench Flow 9.3.2. Verify the Simulation Results
10. Simulate and Compile - Auto-Negotiation and Link Training x
10.1. Auto-Negotiation and Link Training for General Ethernet Mode 10.2. Multirate Auto-Negotiation and Link Training for Reconfigurable Mode AN/LT 10.3. Design Example Features 10.4. Design Example Components 10.5. Simulate the Design Example 10.6. Compile the Design Example
10.5. Simulate the Design Example x
10.5.1. Simulation Testbench Flow 10.5.2. Simulation Output
11. Troubleshoot and Diagnose Issues x
11.1. Enable Diagnostic Lookback Modes 11.2. Troubleshoot the Reset Sequence
11.1. Enable Diagnostic Lookback Modes x
11.1.1. Internal Serial Loopback 11.1.2. Enable MAC Loopback 11.1.3. Enable PCS Loopback 11.1.4. Enable External Loopback 11.1.5. Packet Client Loopback
11.2. Troubleshoot the Reset Sequence x
11.2.1. Debug the Power Up Reset Sequence 11.2.2. Debug the TX Reset Entry Sequence 11.2.3. Debug the TX Reset Exit Sequence 11.2.4. Debug the RX Reset Entry Sequence 11.2.5. Debug the RX Reset Exit Sequence 11.2.6. Debug the Auto Recovery Reset Sequence
12. Appendix A: Functional Description x
12.1. Datapath Description 12.2. GTS Ethernet Hard IP MAC 12.3. PCS, OTN, and FlexE Modes 12.4. Precision Time Protocol Interface 12.5. Auto-Negotiation and Link Training
12.2. GTS Ethernet Hard IP MAC x
12.2.1. MAC TX Datapath 12.2.2. MAC RX Datapath 12.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 12.2.4. Link Fault Signaling 12.2.5. Order of Ethernet Transmission:
12.2.1. MAC TX Datapath x
12.2.1.1. Insert TX Preamble, Start, and SFD 12.2.1.2. Insert Source Address 12.2.1.3. Process Length/Type Field 12.2.1.4. Pad the Client Frame 12.2.1.5. Insert Frame Check Sequence (CRC-32) 12.2.1.6. Generate and Insert Inter-Packet Gap
12.2.2. MAC RX Datapath x
12.2.2.1. Process RX Preamble 12.2.2.2. Check RX Strict SFD 12.2.2.3. Check RX FCS 12.2.2.4. Handle RX Malformed Packet 12.2.2.5. Remove PAD Bytes and FCS Bytes from RX Frames 12.2.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 12.2.2.7. Inter-Packet Gap
12.2.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
12.2.3.1. Conditions Triggering XOFF Frame Transmission 12.2.3.2. Conditions Triggering XON Frame Transmission 12.2.3.3. Pause Control and Generation Interface 12.2.3.4. Pause Control Frame Filtering
12.3. PCS, OTN, and FlexE Modes x
12.3.1. PCS Mode 12.3.2. OTN Mode 12.3.3. FlexE Mode
12.4. Precision Time Protocol Interface x
12.4.1. Features 12.4.2. PTP User Flow 12.4.3. Make PTP UI Adjustments 12.4.4. Reference Time Interval
12.4.2. PTP User Flow x
12.4.2.1. PTP TX User Flow 12.4.2.2. PTP RX User Flow
12.4.3. Make PTP UI Adjustments x
12.4.3.1. Adjust TX UI 12.4.3.2. Adjust RX UI
13. Appendix B: Configuration Registers x
13.1. Ethernet Avalon® Memory-Mapped Interface Address Space 13.2. Packet Client Registers
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs

4.8. Connect the Ethernet Hard IP Reconfiguration Interface

Connect the Ethernet Reconfiguration Interface, an Avalon® MM slave, to an Avalon® MM master, to enable the master to read the control and status address space of the GTS Ethernet Hard IP.
Figure 49. Signals of the Ethernet Hard IP Reconfiguration Interface

For more details on read and write transactions for the Ethernet Avalon® memory-mapped reconfiguration interface, refer to the Transfers section of Avalon® Interface Specifications.

Connect the interface signals according to the rules and description provided in the following table. All of these signals are synchronous to the i_reconfig_clk.

Table 46.  Ethernet Hard IP Reconfiguration Interface Signals
Port Name Width Description
i_reconfig_eth_addr 18 bits Byte address bus for Ethernet control and status registers.
i_reconfig_eth_byteenable 4 bits Byte enable for Ethernet read and write request signals.
i_reconfig_eth_read 1 bit Read request signal for Ethernet control and status registers.
i_reconfig_eth_writedata 32 bits Write request signal for Ethernet control and status registers.
i_reconfig_eth_write 1 bit Write data for Ethernet control and status registers.
o_reconfig_eth_readdata 32 bits Read data from reads to Ethernet control and status registers.
o_reconfig_eth_readdata_valid 1 bit Read data from Ethernet control and status registers is valid.
o_reconfig_eth_waitrequest 1 bit Avalon® memory-mapped interface stalling signal for operations on Ethernet control and status registers.

This interface can access the entire address space of the Ethernet Hard IP. Refer to Appendix B: Configuration Registers for a description of the address space and links to all of the Ethernet Hard IP's status and control registers.

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