GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
10.5.2. Simulation Output
The following sample output illustrates a successful simulation test run for VCS* MX simulator. The script and waveform output is similar for other supported simulators.
# ---TX reset sequence completed ----- # ----RX reset sequence completed ----- --- Starting Data mode after completing AN--- ------IP_INST[0] Test 0; ---Total 16 packets to send---- ------IP_INST[0] Start pkt gen TX----- ------Checking Packet TX/RX result----- ------2 packets Sent; 0 packets Received-------- ------6 packets Sent; 0 packets Received-------- ------10 packets Sent; 3 packets Received------- ------14 packets Sent; 7 packets Received------- ------16 packets Sent; 11 packets Received------- ------ ALL 16 packets Sent out----------------- ------16 packets Sent; 14 packets Received-------- ------16 packets Sent; 16 packets Received-------- ------ ALL 16 packets Received--- ------ TX/RX packet check OK--- ****Starting AVMM Read/Write**** ====>MATCH! Read addr = 00000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 ====>MATCH! Read addr = 00100004, ReaddataValid = 1 Readdata = b1f05663 Expected_Readdata = b1f05663 ====>MATCH! Read addr = 00100008, ReaddataValid = 1 Readdata = 06b97b0d Expected_Readdata = 06b97b0d ====>MATCH! Read addr = 00100080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de ====>MATCH! Read addr = 00300080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de ====>MATCH! Read addr = 00000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 ====>MATCH! Read addr = 00050014, ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 ====>MATCH! Read addr = 0005001c, ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee ====>MATCH! Read addr = 00050014, ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 ====>MATCH! Read addr = 00050018, ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab ====>MATCH! Read addr = 000a5000, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 **** AVMM Read/Write Operation Completed for IP_INST[0]**** **** AVMM Read/Write 50030 **** 0 ====>MATCH! Read addr = 00050030, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 The time now is 2490000000000 ====>MATCH! Read addr = 00050030, ReaddataValid = 1 Readdata = 000001f5 Expected_Readdata = 000001f5 ====>MATCH! Read addr = 00050030, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 **** AVMM Read/Write 50030 DONE ****0 **** AVMM Read/Write 50000[3] ******0 ====>MATCH! Read addr = 00050000, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 ====>MATCH! Read addr = 00050000, ReaddataValid = 1 Readdata = 00000008 Expected_Readdata = 00000008 ====>MATCH! Read addr = 00050000, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 **** AVMM Read/Write 50000[3] DONE ****0 **************** Testbench complete**********************# **
Note: The simulation completion may take a longer time. To confirm that the simulation is progressing successfully, verify the intermediate outputs from the System Console, such as bringing the base and AN/LT IP out of reset, IP reset sequence, AN/LT completion, and others.