GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
3.6. Analog Parameter Options
You can tune the analog functions of GTS PMAs to design high-speed serial protocol solutions by using the transceiver's analog parameter settings. This feature allows you to compensate for signal losses in high-data-rate communications.
To configure the Analog TX and Analog RX parameters of the PMA, access the Analog Parameters tab in the GTS Ethernet Hard IP GUI. When the Ethernet operation mode is set to dynamically reconfigurable, you can configure the analog parameters for each profile separately.
Figure 12. Analog Parameter Options in Parameter Editor
Note: Additionally, you can specify the analog parameters in the .qsf file, which take precedence over the analog parameter settings in the IP GUI. Setting these parameters via the .qsf file overrides the settings in the GUI.
#TX Analog Parameter Configuration set_instance_assignment -name HSSI_PARAMETER "tx_invert_pin=tx_invert_pin_enable" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_post_tap_1=5" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_main_tap=52" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_pre_tap_1=0" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "tx_eq_pre_tap_2=0" -to <TX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> #RX Analog Parameter Configuration set_instance_assignment -name HSSI_PARAMETER "rx_invert_pin=rx_invert_pin_enable" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_external_couple_type=RX_EXTERNAL_COUPLE_TYPE_AC" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_termination_mode=RX_TERMINATION_MODE_GROUNDED" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME> set_instance_assignment -name HSSI_PARAMETER "rx_onchip_termination_setting=RX_ONCHIP_TERMINATION_SETTING_R_2" -to <RX_SERIAL_PIN> -entity <TOP_LEVEL_NAME>
Parameter | Values | Default Setting | Description |
---|---|---|---|
Analog TX | |||
Enable TX P&N Invert |
|
Disable | Invert TX serial outputs P and N pins. |
TX EQ Post Tap 1, 1.0 step size | 0 to 19 | 5 | TX equalization control for Post Tap 1. |
TX EQ Main Tap, 1.0 step size | 0 to 55 | 52 | TX equalization control for Main Tap. |
TX EQ Pre Tap 1, 1.0 step size | 0 to 15 | 0 | TX equalization control for Pre Tap 1. |
TX EQ Pre Tap 2, 1.0 step size | 0 to 7 | 0 | TX equalization control for Pre Tap 2. |
Analog RX | |||
Enable RX P&N Invert 3 |
|
Disable | Invert RX serial input P and N pins. |
RX External Coupling Mode |
|
AC | Specifies the type of external on-board coupling mode. |
Selects value of RX termination mode |
|
GROUNDED | Specifies the RX PMA buffer termination mode. GROUNDED mode is used for AC-coupled links, while DIFFERENTIAL mode is used for DC-coupled links. |
Selects value of RX onchip termination |
|
R_2 (100 ohm) | Selects RX on-chip termination resistor value. |
3 This feature is preliminarily and is planned to be fully supported in a future Quartus® Prime Pro Edition software release.