GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)

The single instance IP design example supports 10GE Ethernet rates and demonstrates the basic functionality of the GTS Ethernet Hard IP with optional FEC.

IP Parameter Settings for 10GE Dynamically Reconfigurable Mode Single Instance Design Example with Optional FEC Table specifies parameter settings used to generate 10GE dynamically reconfigurable mode design example.
Selected IP Parameter Settings Value
Enable Auto-Negotiation and Link Training
Enable Auto-Negotiation and Link Training Off
Simulation Options
Enable fast simulation On
IP Tab-General Options
Ethernet Operation Mode Dynamically Reconfigurable
Number of Secondary Profiles 1
Client interface MAC Avalon® ST
MAC Use Case 1 Port MAC
PMA reference frequency 156.25 MHz
System PLL frequency 322.265625 MHz
Enable Asynchronous Adapter Clocks Off
Use HVIO PLL Off
Enable Dedicated CDR Clock Output Off
PTP Options
Enable IEEE 1588 PTP Off
Profile #0 > Port #0 IP Configuration
Ethernet Mode 10G-1
FEC Mode

None

Profile #0 > Port #0 IP Configuration
Ethernet Mode 10G-1
FEC Mode IEEE 802.3 BASE-R Firecode (CL74)
Example Design Tab
Select Design Single Instance of IP core
Example Design Files
Simulation Off
Synthesis Off
Generated HDL Format
Generated File Format Verilog
Target Development Kit
Select Board

None

Select Device Initialization Clock OSC_CLK_1_125MHz

For more information about steps on how to generate a design example, refer to the Generate GTS EHIP Design Example.