GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs
ID
848477
Date
7/07/2025
Public
1. Overview
2. Install and License the GTS Ethernet Hard IP
3. Configure and Generate Ethernet Hard IP variant
4. Integrate GTS Ethernet Hard IP into Your Application
5. Simulate and Compile (MAC+PCS) Design Example
6. Simulate and Compile (MII PCS Only/PCS66 OTN/PCS66 FlexE) Design Example
7. Simulate and Compile SyncE Design Example
8. Simulate and Compile PTP1588 Design Example
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
10. Simulate and Compile - Auto-Negotiation and Link Training
11. Troubleshoot and Diagnose Issues
12. Appendix A: Functional Description
13. Appendix B: Configuration Registers
14. Appendix C: Document Revision History for the GTS Ethernet Hard IP User Guide: Agilex 3 FPGAs and SoCs
4.1. Implement Required Clocking
4.2. Implement Required Resets
4.3. Connect the Status Interface
4.4. Connect the MAC Avalon Streaming Client Interface
4.5. Connect the MII PCS Only Client Interface
4.6. Connect the PCS66 Client Interface – FlexE and OTN
4.7. Connect the Precision Time Protocol Interface
4.8. Connect the Ethernet Hard IP Reconfiguration Interface
4.9. Connect the Auto-Negotiation and Link Training
4.10. Connect the Multirate Auto-Negotiation and Link Training
4.11. Connect the Dynamically Reconfigurable Ethernet Mode
4.4.1.1. Drive the Ethernet Packet to the TX MAC Avalon Streaming Client Interface with Disabled Preamble Passthrough
4.4.1.2. Drive the Ethernet Packet on the TX MAC Avalon Streaming Client Interface with Enabled Preamble Passthrough
4.4.1.3. Use i_tx_skip_crc to Control Source Address, PAD, and CRC Insertion
4.4.1.4. Assert the i_tx_error to Invalidate a Packet
4.4.2.1. Receive Ethernet Frame on the RX MAC Avalon Streaming Client Interface with Preamble Passthrough Disabled
4.4.2.2. Receive Ethernet Frame with Preamble Passthrough Enabled
4.4.2.3. Receive Ethernet Frame with Remove CRC bytes Disabled
4.4.2.4. Monitor Status and Errors on the RX MAC Avalon Streaming Client Interface
9. Simulate and Compile (Dynamically Reconfigurable Ethernet Mode)
The single instance IP design example supports 10GE Ethernet rates and demonstrates the basic functionality of the GTS Ethernet Hard IP with optional FEC.
Selected IP Parameter Settings | Value |
---|---|
Enable Auto-Negotiation and Link Training | |
Enable Auto-Negotiation and Link Training | Off |
Simulation Options | |
Enable fast simulation | On |
IP Tab-General Options | |
Ethernet Operation Mode | Dynamically Reconfigurable |
Number of Secondary Profiles | 1 |
Client interface | MAC Avalon® ST |
MAC Use Case | 1 Port MAC |
PMA reference frequency | 156.25 MHz |
System PLL frequency | 322.265625 MHz |
Enable Asynchronous Adapter Clocks | Off |
Use HVIO PLL | Off |
Enable Dedicated CDR Clock Output | Off |
PTP Options | |
Enable IEEE 1588 PTP | Off |
Profile #0 > Port #0 IP Configuration | |
Ethernet Mode | 10G-1 |
FEC Mode | None |
Profile #0 > Port #0 IP Configuration | |
Ethernet Mode | 10G-1 |
FEC Mode | IEEE 802.3 BASE-R Firecode (CL74) |
Example Design Tab | |
Select Design | Single Instance of IP core |
Example Design Files | |
Simulation | Off |
Synthesis | Off |
Generated HDL Format | |
Generated File Format | Verilog |
Target Development Kit | |
Select Board | None |
Select Device Initialization Clock | OSC_CLK_1_125MHz |
For more information about steps on how to generate a design example, refer to the Generate GTS EHIP Design Example.
Section Content
Design Example Features
Design Example Components
Simulate the Design Example
Compile the Design Example
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