Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813663
Date 9/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC IP Core 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Altera IP Cores 2.2. Installing and Licensing IP Cores 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC IP Core 2.7. Low Latency Ethernet 10G MAC IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC IP Design Example for Agilex™ 3 and Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. Unidirectional Feature 3.4.8. TX Promiscuous (Transparent) Mode 3.4.9. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Unidirectional Signals 5.5. Avalon® Memory-Mapped Interface Programming Signals 5.6. Avalon® Streaming Data Interfaces 5.7. Avalon® Streaming Flow Control Signals 5.8. Avalon® Streaming Status Interface 5.9. PHY-side Interfaces 5.10. IEEE 1588v2 Interfaces
5.6. Avalon® Streaming Data Interfaces x
5.6.1. Avalon® Streaming TX Data Interface Signals 5.6.2. Avalon® Streaming RX Data Interface Signals 5.6.3. Avalon® Streaming Data Interface Clocks
5.8. Avalon® Streaming Status Interface x
5.8.1. Avalon® Streaming Interface TX Status Signals 5.8.2. Avalon® Streaming Interface RX Status Signals
5.9. PHY-side Interfaces x
5.9.1. XGMII TX Signals 5.9.2. XGMII RX Signals 5.9.3. GMII TX Signals 5.9.4. GMII RX Signals 5.9.5. MII TX Signals 5.9.6. MII RX Signals
5.10. IEEE 1588v2 Interfaces x
5.10.1. IEEE 1588v2 Egress TX Signals 5.10.2. IEEE 1588v2 Ingress RX Signals 5.10.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. Unidirectional Control Registers 6.8. RX Configuration and Status Registers 6.9. ECC Registers 6.10. Statistics Registers 6.11. Timestamp Registers
6.11. Timestamp Registers x
6.11.1. Calculating PHY Total Latency 6.11.2. Calculating Deterministic Latency 6.11.3. PTP Register Configuration
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Recommended Signals for Signal Tap
1. Low Latency Ethernet 10G MAC IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC IP Core
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1. Low Latency Ethernet 10G MAC IP Overview

Updated for:
Intel® Quartus® Prime Design Suite 25.1.1
IP Version 5.1.0

The Low Latency Ethernet 10G MAC IP is a configurable component that implements the IEEE 802.3-2008 specification. To build a complete Ethernet subsystem in an Altera FPGA device and connect it to an external device, you can use the Low Latency Ethernet 10G MAC IP with an Altera FPGA PHY IP or any of the supported PHYs.

The figure below shows a system with the Low Latency Ethernet 10G MAC IP.

Figure 1. Typical Application of Low Latency (LL) Ethernet 10G (10GbE) MAC
Note: Altera FPGAs implement and support the Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multirate Ethernet PHY (PCS + PMA) IPs to interface in a chip-to-chip or chip-to-module channel with external PHY.

Section Content
Features
Release Information
Low Latency Ethernet 10G MAC Operating Modes
Device Family Support
Performance and Resource Utilization

Level Two Title