Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

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ID 813663
Date 9/01/2025
Public
Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC IP Core 5. Interface Signals 6. Configuration Registers 7. Debug Checklist 8. Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives 9. Document Revision History for the Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Altera IP Cores 2.2. Installing and Licensing IP Cores 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC IP Core 2.7. Low Latency Ethernet 10G MAC IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC IP Design Example for Agilex™ 3 and Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. Unidirectional Feature 3.4.8. TX Promiscuous (Transparent) Mode 3.4.9. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Unidirectional Signals 5.5. Avalon® Memory-Mapped Interface Programming Signals 5.6. Avalon® Streaming Data Interfaces 5.7. Avalon® Streaming Flow Control Signals 5.8. Avalon® Streaming Status Interface 5.9. PHY-side Interfaces 5.10. IEEE 1588v2 Interfaces
5.6. Avalon® Streaming Data Interfaces x
5.6.1. Avalon® Streaming TX Data Interface Signals 5.6.2. Avalon® Streaming RX Data Interface Signals 5.6.3. Avalon® Streaming Data Interface Clocks
5.8. Avalon® Streaming Status Interface x
5.8.1. Avalon® Streaming Interface TX Status Signals 5.8.2. Avalon® Streaming Interface RX Status Signals
5.9. PHY-side Interfaces x
5.9.1. XGMII TX Signals 5.9.2. XGMII RX Signals 5.9.3. GMII TX Signals 5.9.4. GMII RX Signals 5.9.5. MII TX Signals 5.9.6. MII RX Signals
5.10. IEEE 1588v2 Interfaces x
5.10.1. IEEE 1588v2 Egress TX Signals 5.10.2. IEEE 1588v2 Ingress RX Signals 5.10.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. Unidirectional Control Registers 6.8. RX Configuration and Status Registers 6.9. ECC Registers 6.10. Statistics Registers 6.11. Timestamp Registers
6.11. Timestamp Registers x
6.11.1. Calculating PHY Total Latency 6.11.2. Calculating Deterministic Latency 6.11.3. PTP Register Configuration
7. Debug Checklist x
7.1. Pre-Debugging Process 7.2. Clock Frequency 7.3. Recommended Reset Handling 7.4. Recommended Signals for Signal Tap
1. Low Latency Ethernet 10G MAC IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC IP Core
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs

1.1. Features

This IP core is designed to the IEEE 802.3–2008 Ethernet Standard available on the IEEE website (www.ieee.org). All LL 10GbE IP core variations include MAC only and are in full-duplex mode. These IP core variations offer the following features:

  • MAC features:
    • Full-duplex MAC in eight operating modes: 10G, 1G/10G, 1G/2.5G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G.
    • Three variations for selected operating modes: MAC TX only block, MAC RX only block, and both MAC TX and MAC RX block.
    • Programmable promiscuous (transparent) mode.
    • Unidirectional feature as specified by IEEE 802.3 (Clause 66).
    • Priority-based flow control (PFC) with programmable pause quanta. PFC supports 2 to 8 priority queues.
  • Interfaces:
    • Client-side—32-bit Avalon® streaming interface.
    • Management—32-bit Avalon® memory-mapped interface.
    • PHY-side—32-bit XGMII for 10 GbE, 16-bit GMII for 2.5 GbE, 8-bit GMII for 1 GbE, or 4-bit MII for 10M/100M.
  • Frame structure control features:
    • Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
    • Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
    • Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications.
    • Supports programmable IPG.
    • Ethernet flow control using pause frames.
    • Programmable maximum length of TX and RX data frames up to 64 Kbytes (KB).
    • Preamble passthrough mode on TX and RX datapaths, which allows user defined preamble in the client frame.
    • Optional padding insertion on the TX datapath and termination on the RX datapath.
  • Frame monitoring and statistics:
    • Optional CRC checking and forwarding on the RX datapath.
    • Optional statistics collection on TX and RX datapaths.
  • Optional timestamping as specified by the IEEE 1588v2 standard for the following configurations:
    • 2.5GbE MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY IP core
    • 1G/2.5GbE MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY IP core
    • 1G/2.5G/10G MAC with 1G/2.5G/5G/10G Multirate Ethernet PHY IP core
    • 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC with 10M/100M/1G/2.5G/5G/10G Multirate Ethernet PHY IP core
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