GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

4.2.2. Connect the GTS Reset Sequencer IP

Instantiate and connect the GTS Reset Sequencer IP to the GTS Ethernet Hard IP . The following subsections describe this process:

The GTS Reset Sequencer IP receives reset requests from the GTS Ethernet Hard IP and grants them based on priority.

Figure 25. Connect to the GTS Reset Sequencer IP
The following table describes the input and output signals of the GTS Reset Sequencer IP:
Table 24.  GTS Reset Sequencer Intel® FPGA IP Signals N: Number of channels used.
Signal Name Width Description
i_src_rs_req N Request from EHIP to GTS Reset Sequencer IP to perform a reset of the target transceiver channel.
i_src_rs_priority N

Binary priority input

  • 0 - Low priority
  • 1 - High priority

This port is used to set priority for a channel that you need to prioritize the reset sequence when there are multiple channels being reset simultaneously. You must tie the input to 0 except for the priority channel which needs to be set to 1.

o_src_rs_grant N Grant from GTS Reset Sequencer IP to EHIP. Asserts when the Reset Sequencer acknowledges the reset request.
o_pma_cu_clk M PMA Control Unit clock output, one per GTS bank for each side of the device. This clock port must be connected as shown in the Connect to the GTS Reset Sequencer IP.
i_refclk_bus_out 1 Input of the GTS Reset Sequencer IP. It indicates the failure of the local or regional reference clock at the left or right transceiver banks.
o_shoreline_refclk_fail_stat 1 Reference clock fail status indication from GTS Reset Sequencer IP to user logic.

Refer to Input Reference Clock Buffer Protection and Implementing the Reset Sequencer IP of the GTS Transceiver PHY User Guide for more functional details on i_refclk_bus_out signal.