GTS Ethernet Hard IP User Guide: Agilex™ 3 FPGAs and SoCs

ID 848477
Date 7/07/2025
Public
Document Table of Contents

4.2.2.1. Requirements and Considerations for GTS Reset Sequencer IP

When designing, it is important to consider the location of the transceiver. Refer to GTS Transceiver Architecture section of GTS Transceiver Direct PHY User Guide.

The GTS Reset Sequencer IP is required when using the GTS Ethernet Hard IP.

Figure 26. Example Use of Reset Sequencer IPThe following diagram shows the transceiver bank with one Reset Sequencer IP in Agilex™ 3 FPGA.