AN 1009: Preserving Nios® II Processor IP for Quartus® Prime Version 24.1 and Newer
ID
839394
Date
3/17/2025
Public
1. AN 1009: Preserving Nios® II Processor IP for Quartus® Prime Version 24.1 and Newer
2. Preserving Nios® II Processor IP in Quartus® Prime Pro Edition Version 24.1 or Newer
3. Preserving Nios® II Processor IP in Quartus® Prime Standard Edition Version 24.1std or Newer
4. Archiving Projects
5. Document Revision History for AN 1009: Preserving Nios® II Processor IP for Quartus® Prime Version 24.1 and Newer
2.2.1.1.1. Limitations on the Preserved Projects in Quartus® Prime Pro Edition version 24.1 and Newer
In QSYS approach, the new projects have the following limitations:
- The Nios® II processor Parameter tab is blank. You cannot change the Nios® II processor, such as switching a Nios® II/e processor to a Nios® II/f processor.
Figure 9. Blank Parameter Tab
- You cannot add or remove the soft IP peripherals or change the system address map in the Platform Designer. This is to ensure the system’s compatibility with the Quartus_1 SOPCINFO earlier.
Figure 10. System MapThe system address map in Quartus_2 remains unchanged compared to the Quartus_1 SOPCINFO file, for example, the JTAG UART IP address map.
- You cannot change any peripherals or systems connecting to the Nios® II processor, including the Clock Bridge, Reset Bridge, and PLL IP Core.
- You must make changes in the older Quartus® Prime software(Quartus_1) and repeat them during the generic component conversion when you migrate to a newer Quartus® Prime software (Quartus_2). Repeat all the steps in Handling Hardware Component in the Quartus® Prime Pro Edition Project.