AN 1009: Preserving Nios® II Processor IP for Quartus® Prime Version 24.1 and Newer

ID 839394
Date 3/17/2025
Public
Document Table of Contents

2.2.1.1. Handling Hardware Component in the Quartus® Prime Pro Edition Project

To preserve the Nios® II processor IP core in the latest Quartus® Prime Pro Edition software projects in Quartus_2, follow these steps:
  1. Ensure that the Nios® II project is working successfully as a Quartus_1 project.
  2. Verify that the QSYS file is added to Project Navigator > Files.
    Figure 4. QSYS File in Project Files
  3. Save a copy of the generated SOPCINFO file from Quartus_1. Label this SOPCINFO as Quartus_1 SOPCINFO file.
    Note: Do not rename the Quartus_1 SOPCINFO file. Renaming Quartus_1 SOPCINFO file prevents the Nios® II processor software project from being opened.
    .
  4. Verify the version for Quartus_1 SOPCINFO using the following methods:
    1. Verify the format version is related to Quartus_1. In the example shown in the figure below, the version is 23.4.79.
      Figure 5. Verifying SOPCINFO Method 1
    2. Verify the className is altera_nios2_gen2 as shown in the following figure.
      Figure 6. Verifying SOPCINFO Method 2
  5. Start the Quartus_1 software and follow these steps:
    1. Open the Nios® II Quartus® Prime project.
    2. Open the Platform Designer system.
    3. Click Generate HDL to generate the processor implementation.
    4. Select the Nios® II processor.
    5. Navigate to the Component Instantiation tab.
    6. Select Implementation Type as Blackbox.
    7. Click Apply.
    8. Save the Platform Designer system.
    Note: You do not need to click Generate HDL or compile the project, as the step is included in the Quartus_2 phase.
    Figure 7. Component Instantiation Tab
  6. Start Quartus_2 software and follow these steps:
    1. Open the Nios® II Quartus® Prime project.
    2. Proceed with the recommended IP Upgrade.
      Note: The Nios® II processor is excluded from IP Upgrade because it is a generic component as defined in the previous step.
      Figure 8. IP Upgrade (with Nios® II processor excluded)
    3. Ensure the IP Upgrade completes.
    4. Open the Platform Designer system.
    5. Click Generate HDL.
    6. Proceed to compile the design in Quartus_2 software.

You have successfully preserved the discontinued Nios® II processor to a newer Quartus® Prime software (Quartus_2). Proceed to configure the design .SOF file into the FPGA devices.