Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

5.4. Power

Table 10.  AGI 022/027 to AGM 032/039 Migration
Power Rails AGM 032/039
VCCIO Migratable with condition2
VREF DNU3
VCCA_IO_Y* Reassign to NC
Table 11.  Voltage Rail Groups for AGI 022/027 to AGM 032/039 Migration
Group 1 Group 2

Group 3a

(Consolidated 1.8v rails)

 Group 3b

VCC

VCCP

VCCL_SDM

VCCH_SDM

VCCH

VCCPLLDIG_SDM

VCCL_HPS

VCCPLLDIG_HPS

VCCLPLL_NOC

VCCPLLDIG_NOC

VCC_HSSI_GXF

VCCERT_FGT_GXF

VCCERT1_FHT_GXF

VCCERT2_FHT_GXF

VCC_HSSI_GXR

VCCE_PLL_ GXR

VCCE_DTS_GXR

VCCRT_GXR

VCCFUSECORE_GXF

VCCFUSEWR_GGXF

VCCEHT_FHT_GXF

VCCED_GXR

VCCCLK_GXR

VCCHFUSE_GXR

VCCPT

VCCPLL_SDM

VCCADC

VCCPLL_HPS

VCCFUSEWR_SDM

VCCIO_SDM

VCCIO_HPS

VCCIO_NOC

VCCPLL_NOC

VCCCLK_GXF

VCCH_FGT_GXF

VCCHFUSE_GXR

VCCH_GXR

VCCIO_PIO

VCCIO_PIO_SDM

VCCRCORE

VCCIO_UIB
Table 12.  Additional Power Rails for AGM 032/039
Power Rails AGI 022/027 AGM 032/039
VCCIO_NOC NC
  • Power rail for AGM 032/039 only
  • 1.8 V I/O power
VCCLPLL_NOC NC
  • Power rail for AGM 032/039 only
  • 0.8 V I/O and PLL digital power
VCCPLLDIG_NOC NC
  • Power rail for AGM 032/039 only
  • 0.8 V PLL digital power
VCCPLL_NOC NC
  • Power rail for AGM 032/039 only
  • 1.8 V PLL analog power
VCCIO_UIB GND
  • Power rail for AGM 032/039 only
  • 1.2 V power
Note: Connect this VCCIO_UIB pin to GND on the board connection for the AGM 032/039 if the UIB is not used.

For successful migration, the board design should be based on the AGM 032/039.

When designing for the device migration, there are options to connect the NC pins to either power, GND, or a signal trace depending on the pin assignment of the devices selected for migration.

Other power rails that are not listed in the previous tables are fully migratable. Refer to the Agilex™ 7 Device Family Pin Connection Guidelines and AN 910: Agilex™ 7 Power Distribution Network Design Guidelines for more information on the regulator sizing, power decoupling design, and power grouping details.

Related Information
2 The migration of this power rail depends on the I/O bank migration conditions. Refer to the GPIO section for more information.
3 Leave VREF pin floating when migrating DDR4 interfaces from AGI 022/027 to AGM 032/039.
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