Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information

Refer to the following tables for detailed Address/Command pin placement within the I/O sub-bank. For the Agilex™ 7 M-series, the top and bottom I/O sub-bank within an I/O bank, has different Address/Command pin placement.

Table 6.  Top I/O Sub-Bank Address/Command Pin Placement
Sub-Bank I/O Index Index within I/O Bank (Top Sub-Bank Index) Index within I/O Lane DDR4 Scheme 1: Component and DIMM (Supports up to 4 ranks for UDIMM/RDIMM/SO-DIMM/Component) DDR4 Scheme 1A: Component, LRDIMM and RDIMM (with base component x16Gb x4DQ/DQS group) DDR4 Scheme 2: Component and DIMM (Supports up to 2 ranks for UDIMM/RDIMM/SO-DIMM/Component) ONLY scheme for HPS EMIF Available to Fabric EMIF as well DDR4 Scheme 3: Component and DIMM, with 3DS (Support 3DS; Supports up to 4 ranks for UDIMM/RDIMM/SO-DIMM/Component) DDR4 Scheme 3A: Component and DIMM, with 3DS (Support 3DS; Supports up to 4 ranks for UDIMM/RDIMM/SO-DIMM/Component)
Lane 7 I/O Sub-Bank with I/O index 48:95 95 11 CK_N_1 CK_N_1 – CK_N_1 CK_N_1
94 10 CK_1 CK_1 – CK_1 CK_1
93 9 CK_N_3
Note: Do not use if planning migration
– – – –
92 8 CK_3
Note: Do not use if planning migration
ALERT_N – – ALERT_N
91 7 CK_N_2
Note: Do not use if planning migration
– – CS_3
Note: Do not use if planning migration
CS_3
Note: Do not use if planning migration
90 6 CK_2
Note: Do not use if planning migration
– – CS_2
Note: Do not use if planning migration
CS_2
Note: Do not use if planning migration
89 5 CKE_3
Note: Do not use if planning migration
– – CKE_3
Note: Do not use if planning migration
CKE_3
Note: Do not use if planning migration
88 4 CKE_2
Note: Do not use if planning migration
– – CKE_2
Note: Do not use if planning migration
CKE_2
Note: Do not use if planning migration
87 3 ODT_3
Note: Do not use if planning migration
– – ODT_3
Note: Do not use if planning migration
ODT_3
Note: Do not use if planning migration
86 2 ODT_2
Note: Do not use if planning migration
– – ODT_2
Note: Do not use if planning migration
ODT_2
Note: Do not use if planning migration
85 1 CS_N_3
Note: Do not use if planning migration
– – C_1
Note: Do not use if planning migration
C_1
Note: Do not use if planning migration
84 0 CS_N_2
Note: Do not use if planning migration
– – C_0 C_0
Lane 6 83 11 PAR_0 PAR_0 PAR_0 PAR_0 PAR_0
82 10 CS_1 CS_1 CS_1 CS_1 CS_1
81 9 CK_N_0 CK_N_0 CK_N_0 CK_N_0 CK_N_0
80 8 CK_0 CK_0 CK_0 CK_0 CK_0
79 7 CKE_1 CKE_1 CKE_1 CKE_1 CKE_1
78 6 CKE_0 CKE_0 CKE_0 CKE_0 CKE_0
77 5 ODT_1 ODT_1 ODT_1 ODT_1 ODT_1
76 4 ODT_0 ODT_0 ODT_0 ODT_0 ODT_0
75 3 ACT_N_0 ACT_N_0 ACT_N_0 ACT_N_0 ACT_N_0
74 2 CS_0 CS_0 CS_0 CS_0 CS_0
73 1 RESET_N_0 RESET_N_0 RESET_N_0 RESET_N_0 RESET_N_0
72 0 BG_1 BG_1 BG_1 BG_1 BG_1
Lane 5 71 11 BG_0 BG_0 BG_0 BG_0 BG_0
70 10 BA_1 BA_1 BA_1 BA_1 BA_1
69 9 BA_0 BA_0 BA_0 BA_0 BA_0
68 8 ALERT_N A_17 ALERT_N ALERT_N A_17
67 7 A_16 A_16 A_16 A_16 A_16
66 6 A_15 A_15 A_15 A_15 A_15
65 5 A_14 A_14 A_14 A_14 A_14
64 4 A_13 A_13 A_13 A_13 A_13
63 3 A_12 A_12 A_12 A_12 A_12
62 2 RZQ Site
61 1 Differential "N-Side" Reference Clock Input Site (LVDS Reference Clock Only)
60 0 Single-Ended or Differential "P-Side" PLL Reference Clock Input Site
Lane 4 59 11 A_11 A_11 A_11 A_11 A_11
58 10 A_10 A_10 A_10 A_10 A_10
57 9 A_9 A_9 A_9 A_9 A_9
56 8 A_8 A_8 A_8 A_8 A_8
55 7 A_7 A_7 A_7 A_7 A_7
54 6 A_6 A_6 A_6 A_6 A_6
53 5 A_5 A_5 A_5 A_5 A_5
52 4 A_4 A_4 A_4 A_4 A_4
51 3 A_3 A_3 A_3 A_3 A_3
50 2 A_2 A_2 A_2 A_2 A_2
49 1 A_1 A_1 A_1 A_1 A_1
48 0 A_0 A_0 A_0 A_0 A_0
Table 7.  Bottom I/O Sub-Bank Address/Command Pin Placement
Sub-Bank I/O Index Index within I/O Bank (Bottom Sub-Bank Index) Index within I/O Lane DDR4 Scheme 1: Component and DIMM (Supports up to 4 ranks for UDIMM/RDIMM/SO-DIMM/Component) DDR4 Scheme 1A: Component, LRDIMM and RDIMM (with base component x16Gb x4DQ/DQS group) DDR4 Scheme 2: Component and DIMM (Supports up to 2 ranks for UDIMM/RDIMM/SO-DIMM/Component) ONLY scheme for HPS EMIF Available to Fabric EMIF as well DDR4 Scheme 3: Component and DIMM, with 3DS (Support 3DS; Supports up to 4 ranks for UDIMM/RDIMM/SO-DIMM/Component) DDR4 Scheme 3A: Component and DIMM, with 3DS (Support 3DS; Supports up to 4 ranks for UDIMM/RDIMM/SO-DIMM/Component)
Lane 3 I/O Sub-Bank with I/O index 0:47 47 11 BG_0 BG_0 BG_0 BG_0 BG_0
46 10 BA_1 BA_1 BA_1 BA_1 BA_1
45 9 BA_0 BA_0 BA_0 BA_0 BA_0
44 8 ALERT_N A_17 ALERT_N ALERT_N A_17
43 7 A_16 A_16 A_16 A_16 A_16
42 6 A_15 A_15 A_15 A_15 A_15
41 5 A_14 A_14 A_14 A_14 A_14
40 4 A_13 A_13 A_13 A_13 A_13
39 3 A_12 A_12 A_12 A_12 A_12
38 2 RZQ Site
37 1 Differential "N-Side" Reference Clock Input Site (LVDS Reference Clock Only)
36 0 Single-Ended or Differential "P-Side" PLL Reference Clock Input Site
Lane 2 35 11 A_11 A_11 BG_0 BG_0 BG_0
34 10 A_10 A_10 BA_1 BA_1 BA_1
33 9 A_9 A_9 BA_0 BA_0 BA_0
32 8 A_8 A_8 A_8 A_8 A_8
31 7 A_7 A_7 A_16 A_16 A_16
20 6 A_6 A_6 A_15 A_15 A_15
29 5 A_5 A_5 A_14 A_14 A_14
28 4 A_4 A_4 A_13 A_13 A_13
27 3 A_3 A_3 A_12 A_12 A_12
26 2 A_2 A_2 A_11 A_11 A_11
25 1 A_1 A_1 A_10 A_10 A_10
24 0 A_0 A_0 BG_1 BG_1 BG_1
Lane 1 23 11 PAR_0 PAR_0 A_11 A_11 A_11
22 10 CS_1 CS_1 A_10 A_10 A_10
21 9 CK_N_0 CK_N_0 A_9 A_9 A_9
20 8 CK_0 CK_0 A_8 A_8 A_8
19 7 CKE_1 CKE_1 A_7 A_7 A_7
18 6 CKE_0 CKE_0 A_6 A_6 A_6
17 5 ODT_1 ODT_1 A_5 A_5 A_5
16 4 ODT_0 ODT_0 A_4 A_4 A_4
15 3 ACT_N_0 ACT_N_0 A_3 A_3 A_3
14 2 CS_0 CS_0 A_2 A_2 A_2
13 1 RESET_N_0 RESET_N_0 RESET_N_0 RESET_N_0 RESET_N_0
12 0 BG_1 BG_1 A_0 A_0 A_0
Lane 0 11 11 CK_N_1 CK_N_1 – CK_N_1 CK_N_1
10 10 CK_1 CK_1 – CK_1 CK_1
9 9 CK_N_3
Note: Do not use if planning migration
– – – –
8 8 CK_3
Note: Do not use if planning migration
ALERT_N – – ALERT_N
7 7 CK_N_2
Note: Do not use if planning migration
– – CS_3
Note: Do not use if planning migration
CS_3
Note: Do not use if planning migration
6 6 CK_2
Note: Do not use if planning migration
– – CD_2
Note: Do not use if planning migration
CD_2
Note: Do not use if planning migration
5 5 CKE_3
Note: Do not use if planning migration
– – CKE_3
Note: Do not use if planning migration
CKE_3
Note: Do not use if planning migration
4 4 CKE_2
Note: Do not use if planning migration
– – CKE_2
Note: Do not use if planning migration
CKE_2
Note: Do not use if planning migration
3 3 ODT3
Note: Do not use if planning migration
– – ODT3
Note: Do not use if planning migration
ODT3
Note: Do not use if planning migration
2 2 ODT2
Note: Do not use if planning migration
– – ODT2
Note: Do not use if planning migration
ODT2
Note: Do not use if planning migration
1 1 CS_N_3
Note: Do not use if planning migration
– – C_1
Note: Do not use if planning migration
C_1
Note: Do not use if planning migration
0 0 CS_N_2
Note: Do not use if planning migration
– – C_0 C_0
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