Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

5.1. I/O PLL

Consider the following changes in the Intel Agilex 7 M-Series devices for your design:
  • I/O bank I/O PLL supports a maximum of 4 output clocks and the fabric-feeding I/O PLL supports a maximum of 7 output clocks.
  • Fabric-feeding I/O PLL also resides in the universal interface bus subsystem (UIBSS) in the Intel Agilex 7 M-Series devices.
  • I/O PLL Type selection is not available, The I/O bank I/O PLL or fabric-feeding I/O PLL is determined by the Quartus® Prime automatically, based on the available locations and the PLL features used. If necessary, use the QSF parameters to set the PLL type.
  • Bandwidth setting selection is not available for users, the Quartus® Prime automatically sets the bandwidth based on the M counter value.
  • Dynamic phase shift is supported only through dynamic reconfiguration.
  • When cascading via dedicated path, you can only select C5 or C6 PLL C-Counter to feed the cascade_out port.
  • When cascading via the core, you must identify the upstream PLL upon instantiation of the PLL.
  • Each PLL can only support one LVDS through outclk_periph port.
  • All PLL input clocks, regardless of sources, goes into either refclk or refclk1. QSF assignments are required to indicate whether clock signal is directly from a dedicated clock pin, the reference clock tree, or the core.
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