Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration

The following table describes the connections required when using HPS or Non-HPS devices for the Agilex™ 7 M-series.

Table 13.  Required Connections when using HPS or Non-HPS Devices for the Agilex™ 7 M-series
Pin HPS Non-HPS
VCCL_HPS VCCL_HPS supplies power to the HPS core. You must still provide power to the HPS power supply. Do not leave floating or connected to GND.
VCCIO_HPS The HPS dedicated I/Os support 1.8V voltage level. You must still provide power to the HPS power supply. Do not leave floating or connected to GND.
VCCPLL_HPS VCCPLL_HPS supplies analog power to the HPS PLLs. You must still provide power to the HPS power supply. Do not leave floating or connected to GND.
VCCPLLDIG_HPS Digital power supply of the PLL in HPS. You must still provide power to the HPS power supply. Do not leave floating or connected to GND.
SDM[HPS_COLD_nRESET]

This is an active low, bidirectional pin.

When asserted externally, this pin will initiate a cold reset procedure to the HPS and its peripherals.

If the cold reset is generated from internal sources, the SDM will switch this pin to output and drive a pulse to indicate reset.

Do not use this optional SDM signal.
JTAG_TCK

HPS JTAG test clock input pin.

Can be selected on one of the HPS_IOA/B pins.

 Cannot be used on the HPS_IOA/B pins.
JTAG_TMS

HPS JTAG test mode select input pin.

Can be selected on one of the HPS_IOA/B pins.

 Cannot be used on the HPS_IOA/B pins.
JTAG_TDO

HPS JTAG test data output pin.

Can be selected on one of the HPS_IOA/B pins.

 Cannot be used on the HPS_IOA/B pins.
JTAG_TDI

HPS JTAG test data input pin.

Can be selected on one of the HPS_IOA/B pins.

 Cannot be used on the HPS_IOA/B pins.
HPS_IOA_[1..24] General purpose input and output.

These pins are in tri-state mode with a weak pull-up enabled.

Ensure that the weak high state of each pin does not cause issues with external circuitry. If it might, isolate with a 0Ω resistor that is depopulated on the board.

HPS_IOB_[1..24] General purpose input and output.

These pins are in tri-state mode with a weak pull-up enabled.

Ensure that the weak high state of each pin does not cause issues with external circuitry. If it might, isolate with a 0Ω resistor that is depopulated on the board.

Level Two Title