Device Migration Guidelines for Agilex™ 7 R31B Package

Download PDF
ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

5.5.2. LVDS SERDES Performance and Feature Change Comparison

Feature AGI022/027 AGM032/039
LVDS SERDES Data Rate 150 Mbps – 1600 Mbps 600 Mbps – 1600 Mbps
SERDES Factor 3 to 10 4 or 8
Maximum number of channels per bank
  • 24 for TX, RX Non-DPA, and RX-FIFO
  • 12 for CDR
  • 47 for TX, RX Non-DPA and RX-FIFO
  • 12 for CDR
External PLL Supported (can connect up to 2 LVDS SERDES IP at a time) Supported (can only connect to 1 LVDS SERDES IP at a time)

Ensure that the AGI 022/027 FPGA design uses LVDS SERDES feature compatible with the AGM 032/039 support.

Example:
  • Use LVDS SERDES at a data rate beyond 600 Mbps in the AGI 022/027 FPGA design to ensure compatibility with AGM 032/039 LVDS SERDES data rate support.
  • Only use SERDES factor 4 or 8 in the AGI 022/027 FPGA design to ensure minimum design change is required when migrating to the AGM 032/039 design.
  • When using external PLL, connect the PLL to a single LVDS SERDES IP only in AGI 022/027 to ensure sufficient PLL resources are available when migrating to AGM 032/039.

Section Content
LVDS SERDES IP Count Per Bank
Unused LVDS SERDES Pins

Level Two Title