Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series

The following table shows the pin index mapping for both the Agilex™ 7 I-Series and the Agilex™ 7 M-Series sub-banks. Refer to the Pin-Out Files for Intel® FPGAs for the pin index of each I/O bank of a specific Agilex™ 7 part.

Table 4.  Pin Index Mapping
Pin Index Lane Sub-bank Location
0–11 0 Bottom
12–23 1
24–35 2
36–47 3
48–59 0 Top
60–71 1
72–83 2
84–95 3

The following table provides guidelines on pin placement for DDR4 external memory interfaces between the Agilex™ 7 I-Series and the Agilex™ 7 M-Series.

Table 5.  Address/Command Sub-bank I/O Pin Index
Pin Name Agilex™ 7 I-Series Sub-bank I/O Index Agilex™ 7 M-Series Sub-bank I/O Index Placement in Top or Bottom I/O Sub-Bank
RZQ 26 38 Bottom
74 62 Top
PLL Reference Clock Input 24 (P-side) and 25 (N-side) 36 (P-side) and 37 (N-side) Bottom
72 (P-side) and 73 (N-side) 60 (P-side) and 61 (N-side) Top
  • For Agilex™ 7 M-Series, Address/Command pin placement within I/O sub-bank (Top I/O sub-bank and Bottom I/O sub-bank) are not identical as in Agilex™ 7 I-Series. Address/Command pin placement within sub-bank differs from index 47:0 to index 95:48. As all the sub-banks are capable of functioning as the address and command bank, care needs to be taken when migrating an Address/Command I/O sub-bank from Top-to-Bottom or Bottom-to-Top.
  • Sub-bank I/O index changes are only applicable during Quartus® Prime pin assignment for DDR4. There is no change to the package ball name or location.
    • Package ball locations correspond between all Agilex™ 7 I- and M-Series devices for which migration is possible.
  • Address/Command Scheme with 4 I/O Lanes and Address/Command Scheme with 3 I/O Lanes have minimum changes to pin placement (with the exception of those mentioned in the previous table).

Section Content
Agilex 7 I-Series EMIF Address/Command Pin Information

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