Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

5.2.1. Migration Path

The migration path from AGI 022/AGI 027 to AGM 032/AGM 039 involves migrating the same set of pin locations in an I/O lane from one GPIO bank to another different GPIO-B bank location. The general-purpose function of these pins, such as general I/O and RZQ, remain the same according to the pin location after the migration. Refer to following table to identify the I/O lane migration path:

Table 8.  I/O Lane Migration Path from AGI 022/AGI 027 to AGM 032/AGM 039
AGI 022, AGI 027 AGM 032, AGM 039
I/O Bank Pin Index I/O Bank Pin Index
3A P95:P84 3A_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P59:P48 P83:P72
3C P47:P36 3C_B P11:P0
P35:P24 P47:P36
P23:P12 P35:P24
P11:P0 P23:P12
P95:P84 3C_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
3D P95:P84 3D_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P59:P48 P83:P72
P47:P36 3D_B P11:P0
P35:P24 P47:P36
P23:P12 P35:P24
P11:P0 P23:P12
3B P95:P84 3B_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P47:P36 3B_B P11:P0
P35:P24 P47:P36
P23:P12 P35:P24
P11:P0 P23:P12
2F P95:P84 2B_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P59:P48 P83:P72
P47:P36 2B_B P11:P0
P35:P24 P47:P36
P23:P12 P35:P24
P11:P0 P23:P12
2C P95:P84 2C_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P59:P48 P83:P72
P47:P36 2C_B P11:P0
P35:P24 P47:P36
P23:P12 P35:P24
P11:P0 P23:P12
2D P95:P84 2D_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P59:P48 P83:P72
P47:P36 2D_B P11:P0
P35:P24 P47:P36
P23:P12 P35:P24
P11:P0 P23:P12
2E P95:P84 2A_T P95:P84
P83:P72 P71:P60
P71:P60 P59:P48
P59:P48 P83:P72
P23:P12 2A_B P35:P24
P11:P0 P23:P12

For example:

When migrating I/O lane in bank 3D with pin index P83:P72 from AGI 022 to AGM 032, the bank location and pin index of the pins in this I/O lane change from bank 3D in AGI 022 to bank 3D_T with pin index P71:P60 in AGM 032.

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