Device Migration Guidelines for Agilex™ 7 R31B Package

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ID 826356
Date 6/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. External Memory Interface 3. I/O Lane Number and I/O Pin Index Mapping 4. Package Height Difference 5. AGI 022/027 to AGM 032/039 Migration 6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration 7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package
2. External Memory Interface x
2.1. Eligible Migration and System Compatibility 2.2. Key Migration Considerations 2.3. DDR4 Interface Design/Migration Considerations 2.4. EMIF Architecture Differences
2.4. EMIF Architecture Differences x
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series 2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series
2.4.1. Key Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.1.1. I/O Subsystem 2.4.1.2. HPS EMIF Subsystem
2.4.2. Address/Command Pin Index Changes between Agilex™ 7 I-Series and Agilex™ 7 M-Series x
2.4.2.1. Agilex™ 7 I-Series EMIF Address/Command Pin Information
5. AGI 022/027 to AGM 032/039 Migration x
5.1. I/O PLL 5.2. GPIO 5.3. External Memory Interface 5.4. Power 5.5. LVDS SERDES 5.6. Temperature Sensor
5.2. GPIO x
5.2.1. Migration Path 5.2.2. VCCIO_PIO Voltage Supplies 5.2.3. I/O Types and Standards 5.2.4. I/O Feature 5.2.5. Design Guidelines
5.3. External Memory Interface x
5.3.1. EMIF IP 5.3.2. Data and Data Strobe Pin Index Changes
5.3.2. Data and Data Strobe Pin Index Changes x
5.3.2.1. AGI 022/027 Pin Placement Restrictions when Migrating to AGM 032/039
5.5. LVDS SERDES x
5.5.1. LVDS SERDES IP 5.5.2. LVDS SERDES Performance and Feature Change Comparison
5.5.2. LVDS SERDES Performance and Feature Change Comparison x
5.5.2.1. LVDS SERDES IP Count Per Bank 5.5.2.2. Unused LVDS SERDES Pins
1. Introduction
2. External Memory Interface
3. I/O Lane Number and I/O Pin Index Mapping
4. Package Height Difference
5. AGI 022/027 to AGM 032/039 Migration
6. AGM 032/039 (HPS) to AGM 032/039 (Non-HPS) Migration
7. Document Revision History for Device Migration Guidelines for Agilex™ 7 R31B Package

2.3. DDR4 Interface Design/Migration Considerations

The following table shows the maximum number of DDR4 interfaces, with different interface width, for both 3 I/O lanes and 4 I/O lanes address/command schemes. It also separately highlights HPS EMIF and Fabric EMIF counts.

Table 2.  Maximum number of DDR4 interfaces for R31B Agilex™ 7 I-series to Agilex™ 7 M-series Migration
Device/Package Migration Avalon® Streaming Interface Configuration Scheme DDR I/O Supported DDR40 Interfaces DDR72 Compact (3 Lane A/C) DDR72 (4 Lane A/C)
Fabric EMIF Fabric and HPS EMIF Fabric EMIF Fabric and HPS EMIF Fabric EMIF Fabric and HPS EMIF
AGI 022/027 No (standalone) No 720 5 4 + HPS (x72/x64) 4 3 + HPS (x72/x64) 4 3 + HPS (x72/x64)
No 720 5 4 + HPS (x40 and less) 3 3 + HPS (x40 and less) 3 3 + HPS (x40 and less)
16, 32 672 4 3 + HPS (x72/x64) 3 2 + HPS (x72/x64) 3 2 + HPS (x72/x64)
16, 32 672 4 3 + HPS (x40 and less) 3 2 + HPS (x40 and less) 3 2 + HPS (x40 and less)
AGM 032/039 No (standalone) No 720 5 4 + HPS (x40 and less) 4 2 + HPS (x40 and less) 4 3 + HPS (x40 and less)
16, 32 672 4 3 + HPS (x40 and less) 3 2 + HPS (x40 and less) 3 2 + HPS (x40 and less)
AGI 022/027 to AGM 032/039 Vertical 1 No 720 5 4 + HPS (x40 and less) 4 3 + HPS (x40 and less) 4 3 + HPS (x40 and less)
16, 32 672 4 3 + HPS (x40 and less) 3 2 + HPS (x40 and less) 3 2 + HPS (x40 and less)
AGI 022/027 to AGM 032/039 Vertical1 No 432 4 4 + HPS (x40 and less) 2 2 + HPS (x40 and less) 1 1 + HPS (x40 and less)
16, 32 432 4 3 + HPS (x40 and less) 2 2 + HPS (x40 and less) 1 1 + HPS (x40 and less)
1 Migration between FPGA products of different core logic densities in the same package ball count.
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