Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.10.2.65. ter_lo

Table 111.  address=0x0160
Field Bits Access Default Description
ter [31:0] Read 0 Transaction Error Count (TER): This counter increments by 1 for every UI on the DQ bus that has an error, regardless of the number of DQ pins in error within that UI. The TER DQ mask register controls which DQ pins are monitored for errors. TER can be used to calculate BER (Bit Error Count) by monitoring a single DQ pin.