Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.10.1.16. driver_error_bitmask_3

Table 45.  address=0x00CC
Field Bits Access Default Description
driver_error_bitmask [31:0] Read 0 Each bit indicates ‘error’ status of each corresponding driver. [127:96]