Visible to Intel only — GUID: group__group__compiler__mem__axi4__driver_1ga20c6f63ab74d46b46b9b87bef1007823
Ixiasoft
Visible to Intel only — GUID: group__group__compiler__mem__axi4__driver_1ga20c6f63ab74d46b46b9b87bef1007823
Ixiasoft
5.2.2.5. data_eq_dq_op
Usage
def pyhydra.ipkits.hydra.driver_mem_axi4.driver_compiler.MemAxi4Driver.data_eq_dq_op (cls, **kwargs)
Description
The DQ ALU generator generates the xDATA pattern.
There can be multiple DQ ALUs, each outputs a configurable pattern observable on a DRAM's DQ pin.
For the following input arguments, substitute <i> with the index of the DQ ALU. You can supply a variable number of arguments to configure distinct ALUs.
Parameters
- dq<i>_start
-
Starting value of the ALU. Set to None to reuse the ALU output from the preceding instruction.
- dq<i>_alu
-
List of ALU operations to derive subsequent values. Set to None to resume the ALU operation sequence from the preceding instruction. Legal ALU operations are:
Returns
Compiler IR object