Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817758
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Test Engine FPGA IP 2. Test Engine IP - Introduction 3. Parameterizing the Test Engine IP 4. Test Engine IP - Interface Signals 5. Test Engine IP - Software 6. Test Engine IP - Limitations 7. Document Revision History for the Test Engine FPGA IP User Guide
1. About the Test Engine FPGA IP x
1.1. Release Information
2. Test Engine IP - Introduction x
2.1. Test Engine IP Feature Support
3. Parameterizing the Test Engine IP x
3.1. Parameters 3.2. Drivers Parameters 3.3. Remote Access Parameters
3.2. Drivers Parameters x
3.2.1. CSR AXI4-Lite Driver Parameters 3.2.2. Memory AXI4 Driver Parameters 3.2.3. Memory Status Driver Parameters 3.2.4. Memory Reset Driver Parameters 3.2.5. CAM AXI4-Stream Driver Parameters
4. Test Engine IP - Interface Signals x
4.1. Remote Interface Signals 4.2. I/O PLL Interface Signals 4.3. Status Interface Signals 4.4. Global CSR interface Signals 4.5. Memory AXI4 Driver Interface Signals 4.6. CSR AXI-Lite Driver Interface Signals 4.7. Memory Status Driver Interface Signals 4.8. Memory Reset Driver Interface Signals 4.9. CAM AXI-Stream Driver Interface Signals 4.10. Registers
4.10. Registers x
4.10.1. Global Control Registers 4.10.2. Memory AXI4 Driver Registers 4.10.3. CSR AXI4-Lite Driver Registers 4.10.4. Memory Status Driver Registers 4.10.5. Memory Reset Driver Registers 4.10.6. CAM AXI4-Stream Driver Registers
4.10.1. Global Control Registers x
4.10.1.1. version_0 4.10.1.2. version_1 4.10.1.3. ctrl_status_0 4.10.1.4. driver_ctrl_status_1 4.10.1.5. driver_run_bitmask_0 4.10.1.6. driver_run_bitmask_1 4.10.1.7. driver_run_bitmask_2 4.10.1.8. driver_run_bitmask3 4.10.1.9. driver_done_bitmask_0 4.10.1.10. driver_done_bitmask_1 4.10.1.11. driver_done_bitmask_2 4.10.1.12. driver_done_bitmask_3 4.10.1.13. driver_error_bitmask_0 4.10.1.14. driver_error_bitmask_1 4.10.1.15. driver_error_bitmask_2 4.10.1.16. driver_error_bitmask_3
4.10.2. Memory AXI4 Driver Registers x
4.10.2.1. version_lo 4.10.2.2. version_hi 4.10.2.3. ctrl_stat_lo 4.10.2.4. ctrl_stat_hi 4.10.2.5. scratchpad_lo 4.10.2.6. scratchpad_hi 4.10.2.7. wr_log_ram_stat_lo 4.10.2.8. wr_log_ram_stat_hi 4.10.2.9. wr_log_ram_ctrl_lo 4.10.2.10. wr_log_ram_ctrl_hi 4.10.2.11. rd_log_ram_stat_lo 4.10.2.12. rd_log_ram_stat_hi 4.10.2.13. rd_log_ram_ctrl_lo 4.10.2.14. rd_log_ram_ctrl_hi 4.10.2.15. wr_err_counters_0_lo 4.10.2.16. wr_err_counters_0_hi 4.10.2.17. rd_err_counters_0_lo 4.10.2.18. rd_err_counters_0_hi 4.10.2.19. rd_err_counters_1_lo 4.10.2.20. rd_err_counters_1_hi 4.10.2.21. rd_pnf_0_lo 4.10.2.22. rd_pnf_0_hi 4.10.2.23. rd_pnf_1_lo 4.10.2.24. rd_pnf_1_hi 4.10.2.25. rd_pnf_2_lo 4.10.2.26. rd_pnf_2_hi 4.10.2.27. rd_pnf_3_lo 4.10.2.28. rd_pnf_3_hi 4.10.2.29. rd_pnf_4_lo 4.10.2.30. rd_pnf_4_hi 4.10.2.31. rd_pnf_5_lo 4.10.2.32. rd_pnf_5_hi 4.10.2.33. rd_pnf_6_lo 4.10.2.34. rd_pnf_6_hi 4.10.2.35. rd_pnf_7_lo 4.10.2.36. rd_pnf_7_hi 4.10.2.37. rd_pnf_8_lo 4.10.2.38. rd_pnf_8_hi 4.10.2.39. rd_pnf_9_lo 4.10.2.40. rd_pnf_9_hi 4.10.2.41. rd_pnf_10_lo 4.10.2.42. rd_pnf_10_hi 4.10.2.43. rd_pnf_11_lo 4.10.2.44. rd_pnf_11_hi 4.10.2.45. rd_pnf_12_lo 4.10.2.46. rd_pnf_12_hi 4.10.2.47. rd_pnf_13_lo 4.10.2.48. rd_pnf_13_hi 4.10.2.49. rd_pnf_14_lo 4.10.2.50. rd_pnf_14_hi 4.10.2.51. rd_pnf_15_lo 4.10.2.52. rd_pnf_15_hi 4.10.2.53. rd_pnf_16_lo 4.10.2.54. rd_pnf_16_hi 4.10.2.55. rd_pnf_17_lo 4.10.2.56. rd_pnf_17_hi 4.10.2.57. rd_pnf_18_lo 4.10.2.58. rd_pnf_18_hi 4.10.2.59. rd_pnf_19_lo 4.10.2.60. rd_pnf_19_hi 4.10.2.61. ter_dq_mask_0_lo 4.10.2.62. ter_dq_mask_0_hi 4.10.2.63. ter_dq_mask_1_lo 4.10.2.64. ter_dq_mask_1_hi 4.10.2.65. ter_lo 4.10.2.66. ter_hi
5. Test Engine IP - Software x
5.1. Overview 5.2. Python library 5.3. User programs 5.4. System Console library
5.2. Python library x
5.2.1. CSR AXI4-Lite Driver APIs 5.2.2. Memory AXI4 Driver APIs 5.2.3. General compiler APIs
5.2.1. CSR AXI4-Lite Driver APIs x
5.2.1.1. read_cmd 5.2.1.2. write_cmd
5.2.2. Memory AXI4 Driver APIs x
5.2.2.1. dq_alu_echo_op 5.2.2.2. dq_alu_invert_op 5.2.2.3. dq_alu_rotate_op 5.2.2.4. dq_alu_prbs_op 5.2.2.5. data_eq_dq_op 5.2.2.6. data_eq_raw_op 5.2.2.7. data_eq_addr_op 5.2.2.8. data_eq_id_op 5.2.2.9. dm_alu_echo_op 5.2.2.10. dm_alu_invert_op 5.2.2.11. dm_alu_rotate_op 5.2.2.12. dm_alu_prbs_op 5.2.2.13. strb_eq_dm_op 5.2.2.14. strb_eq_raw_op 5.2.2.15. addr_alu_echo_op 5.2.2.16. addr_alu_incr_op 5.2.2.17. addr_alu_rand_op 5.2.2.18. addr_op 5.2.2.19. write_worker_op 5.2.2.20. read_worker_op 5.2.2.21. write_cmd 5.2.2.22. read_cmd 5.2.2.23. wait_writes_cmd 5.2.2.24. wait_reads_cmd 5.2.2.25. sleep_cmd 5.2.2.26. driver_post_cmd 5.2.2.27. driver_wait_cmd 5.2.2.28. parallel_cmd 5.2.2.29. loop_cmd
5.2.3. General compiler APIs x
5.2.3.1. get_drivers 5.2.3.2. attach 5.2.3.3. dump
5.3. User programs x
5.3.1. Programs for Memory AXI4 Driver 5.3.2. Programs for CSR AXI4-Lite Driver
5.3.1. Programs for Memory AXI4 Driver x
5.3.1.1. Basic tutorials 5.3.1.2. Advanced tutorials 5.3.1.3. EMIF traffic patterns (for IO96B architecture) 5.3.1.4. HBM2E traffic patterns 5.3.1.5. MemSS traffic patterns (for IO96A architecture) 5.3.1.6. gencmd
5.3.1.1. Basic tutorials x
5.3.1.1.1. tut1_block_rw 5.3.1.1.2. tut2_byteen_test 5.3.1.1.3. tut3_instr_resume 5.3.1.1.4. tut4_parallel_rw 5.3.1.1.5. tut5_multi_id 5.3.1.1.6. tut6_custom_bw 5.3.1.1.7. tut7_driver_sync
5.3.1.2. Advanced tutorials x
5.3.1.2.1. adv1_basic_rw 5.3.1.2.2. adv2_addr_fields 5.3.1.2.3. adv3_instr_resume
5.3.1.3. EMIF traffic patterns (for IO96B architecture) x
5.3.1.3.1. emif_tg_emulation 5.3.1.3.2. emif_tg_emulation_lite 5.3.1.3.3. emif_tg_emulation_long 5.3.1.3.4. emif_tg_emulation_inf 5.3.1.3.5. emif_narrow_transfer
5.3.1.4. HBM2E traffic patterns x
5.3.1.4.1. hbm_simulation1 5.3.1.4.2. hbm_simulation
5.3.1.5. MemSS traffic patterns (for IO96A architecture) x
5.3.1.5.1. memss_default
5.3.2. Programs for CSR AXI4-Lite Driver x
5.3.2.1. HBM2E traffic patterns 5.3.2.2. MemSS traffic patterns (for IO96A architecture)
5.3.2.1. HBM2E traffic patterns x
5.3.2.1.1. hbm_simulation1
5.3.2.2. MemSS traffic patterns (for IO96A architecture) x
5.3.2.2.1. memss_default
5.4. System Console library x
5.4.1. testengine_num_drivers 5.4.2. testengine_driver_list 5.4.3. testengine_run 5.4.4. testengine_reset 5.4.5. testengine_get_errors 5.4.6. testengine_get_done 5.4.7. testengine_status 5.4.8. testengine_reprogram 5.4.9. testengine_axi4_parse_errors
1. About the Test Engine FPGA IP
2. Test Engine IP - Introduction
3. Parameterizing the Test Engine IP
4. Test Engine IP - Interface Signals
5. Test Engine IP - Software
6. Test Engine IP - Limitations
7. Document Revision History for the Test Engine FPGA IP User Guide

4.10.2. Memory AXI4 Driver Registers

Table 46.  Memory AXI4 Driver Summary
Register Name Address Offset Description
version_lo 0x0060

Driver Version
version_hi 0x0064
ctrl_stat_lo 0x0068 Driver Control and Status
ctrl_stat_hi 0x006C
scratchpad_lo 0x0070

Scratch Pad Registers

These contain registers that can be written with any value and read back to the user. These registers are primarily for testing Read/Write access through the sideband interface.
scratchpad_hi 0x0074
wr_log_ram_stat_lo 0x0078 Write Log RAM status.
wr_log_ram_stat_hi 0x007C
wr_log_ram_ctrl_lo 0x0080

Write Log RAM control.
wr_log_ram_ctrl_hi 0x0084
rd_log_ram_stat_lo 0x0088 Read Log RAM status.
rd_log_ram_stat_hi 0x008C
rd_log_ram_ctrl_lo 0x0090 Read Log RAM control.
rd_log_ram_ctrl_hi 0x0094
wr_err_counters_0_lo 0x0098 Write response error counters.
wr_err_counters_0_hi 0x009C
rd_err_counters_0_lo 0x00A0 Read response error counters.
rd_err_counters_0_hi 0x00A4
rd_err_counters_1_lo 0x00A8
rd_err_counters_1_hi 0x00AC
rd_pnf_0_lo 0x00B0 Read response PNF.
rd_pnf_0_hi 0x00B4
rd_pnf_1_lo 0x00B8
rd_pnf_1_hi 0x00BC
rd_pnf_2_lo 0x00C0
rd_pnf_2_hi 0x00C4
rd_pnf_3_lo 0x00C8
rd_pnf_3_hi 0x00CC
rd_pnf_4_lo 0x00D0
rd_pnf_4_hi 0x00D4
rd_pnf_5_lo 0x00D8
rd_pnf_5_hi 0x00DC
rd_pnf_6_lo 0x00E0
rd_pnf_6_hi 0x00E4
rd_pnf_7_lo 0x00E8
rd_pnf_7_hi 0x00EC
rd_pnf_8_lo 0x00F0
rd_pnf_8_hi 0x00F4
rd_pnf_9_lo 0x00F8
rd_pnf_9_hi 0x00FC
rd_pnf_10_lo 0x0100
rd_pnf_10_hi 0x0104
rd_pnf_11_lo 0x0108
rd_pnf_11_hi 0x010C
rd_pnf_12_lo 0x0110
rd_pnf_12_hi 0x0114
rd_pnf_13_lo 0x0118
rd_pnf_13_hi 0x011C
rd_pnf_14_lo 0x0120
rd_pnf_14_hi 0x0124
rd_pnf_15_lo 0x0128
rd_pnf_15_hi 0x012C
rd_pnf_16_lo 0x0130
rd_pnf_16_hi 0x0134
rd_pnf_17_lo 0x0138
rd_pnf_17_hi 0x013C
rd_pnf_18_lo 0x0140
rd_pnf_18_hi 0x0144
rd_pnf_19_lo 0x0148
rd_pnf_19_hi 0x014C
ter_dq_mask_0_lo 0x0150 TER DQ mask
ter_dq_mask_0_hi 0x0154
ter_dq_mask_1_lo 0x0158
ter_dq_mask_1_hi 0x015C
ter_lo 0x0160 TER counter
ter_hi 0x0164

Section Content
version_lo
version_hi
ctrl_stat_lo
ctrl_stat_hi
scratchpad_lo
scratchpad_hi
wr_log_ram_stat_lo
wr_log_ram_stat_hi
wr_log_ram_ctrl_lo
wr_log_ram_ctrl_hi
rd_log_ram_stat_lo
rd_log_ram_stat_hi
rd_log_ram_ctrl_lo
rd_log_ram_ctrl_hi
wr_err_counters_0_lo
wr_err_counters_0_hi
rd_err_counters_0_lo
rd_err_counters_0_hi
rd_err_counters_1_lo
rd_err_counters_1_hi
rd_pnf_0_lo
rd_pnf_0_hi
rd_pnf_1_lo
rd_pnf_1_hi
rd_pnf_2_lo
rd_pnf_2_hi
rd_pnf_3_lo
rd_pnf_3_hi
rd_pnf_4_lo
rd_pnf_4_hi
rd_pnf_5_lo
rd_pnf_5_hi
rd_pnf_6_lo
rd_pnf_6_hi
rd_pnf_7_lo
rd_pnf_7_hi
rd_pnf_8_lo
rd_pnf_8_hi
rd_pnf_9_lo
rd_pnf_9_hi
rd_pnf_10_lo
rd_pnf_10_hi
rd_pnf_11_lo
rd_pnf_11_hi
rd_pnf_12_lo
rd_pnf_12_hi
rd_pnf_13_lo
rd_pnf_13_hi
rd_pnf_14_lo
rd_pnf_14_hi
rd_pnf_15_lo
rd_pnf_15_hi
rd_pnf_16_lo
rd_pnf_16_hi
rd_pnf_17_lo
rd_pnf_17_hi
rd_pnf_18_lo
rd_pnf_18_hi
rd_pnf_19_lo
rd_pnf_19_hi
ter_dq_mask_0_lo
ter_dq_mask_0_hi
ter_dq_mask_1_lo
ter_dq_mask_1_hi
ter_lo
ter_hi

Level Two Title