Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

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ID 817758
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. About the Test Engine FPGA IP 2. Test Engine IP - Introduction 3. Parameterizing the Test Engine IP 4. Test Engine IP - Interface Signals 5. Test Engine IP - Software 6. Test Engine IP - Limitations 7. Document Revision History for the Test Engine FPGA IP User Guide
1. About the Test Engine FPGA IP x
1.1. Release Information
2. Test Engine IP - Introduction x
2.1. Test Engine IP Feature Support
3. Parameterizing the Test Engine IP x
3.1. Parameters 3.2. Drivers Parameters 3.3. Remote Access Parameters
3.2. Drivers Parameters x
3.2.1. CSR AXI4-Lite Driver Parameters 3.2.2. Memory AXI4 Driver Parameters 3.2.3. Memory Status Driver Parameters 3.2.4. Memory Reset Driver Parameters 3.2.5. CAM AXI4-Stream Driver Parameters
4. Test Engine IP - Interface Signals x
4.1. Remote Interface Signals 4.2. I/O PLL Interface Signals 4.3. Status Interface Signals 4.4. Global CSR interface Signals 4.5. Memory AXI4 Driver Interface Signals 4.6. CSR AXI-Lite Driver Interface Signals 4.7. Memory Status Driver Interface Signals 4.8. Memory Reset Driver Interface Signals 4.9. CAM AXI-Stream Driver Interface Signals 4.10. Registers
4.10. Registers x
4.10.1. Global Control Registers 4.10.2. Memory AXI4 Driver Registers 4.10.3. CSR AXI4-Lite Driver Registers 4.10.4. Memory Status Driver Registers 4.10.5. Memory Reset Driver Registers 4.10.6. CAM AXI4-Stream Driver Registers
4.10.1. Global Control Registers x
4.10.1.1. version_0 4.10.1.2. version_1 4.10.1.3. ctrl_status_0 4.10.1.4. driver_ctrl_status_1 4.10.1.5. driver_run_bitmask_0 4.10.1.6. driver_run_bitmask_1 4.10.1.7. driver_run_bitmask_2 4.10.1.8. driver_run_bitmask3 4.10.1.9. driver_done_bitmask_0 4.10.1.10. driver_done_bitmask_1 4.10.1.11. driver_done_bitmask_2 4.10.1.12. driver_done_bitmask_3 4.10.1.13. driver_error_bitmask_0 4.10.1.14. driver_error_bitmask_1 4.10.1.15. driver_error_bitmask_2 4.10.1.16. driver_error_bitmask_3
4.10.2. Memory AXI4 Driver Registers x
4.10.2.1. version_lo 4.10.2.2. version_hi 4.10.2.3. ctrl_stat_lo 4.10.2.4. ctrl_stat_hi 4.10.2.5. scratchpad_lo 4.10.2.6. scratchpad_hi 4.10.2.7. wr_log_ram_stat_lo 4.10.2.8. wr_log_ram_stat_hi 4.10.2.9. wr_log_ram_ctrl_lo 4.10.2.10. wr_log_ram_ctrl_hi 4.10.2.11. rd_log_ram_stat_lo 4.10.2.12. rd_log_ram_stat_hi 4.10.2.13. rd_log_ram_ctrl_lo 4.10.2.14. rd_log_ram_ctrl_hi 4.10.2.15. wr_err_counters_0_lo 4.10.2.16. wr_err_counters_0_hi 4.10.2.17. rd_err_counters_0_lo 4.10.2.18. rd_err_counters_0_hi 4.10.2.19. rd_err_counters_1_lo 4.10.2.20. rd_err_counters_1_hi 4.10.2.21. rd_pnf_0_lo 4.10.2.22. rd_pnf_0_hi 4.10.2.23. rd_pnf_1_lo 4.10.2.24. rd_pnf_1_hi 4.10.2.25. rd_pnf_2_lo 4.10.2.26. rd_pnf_2_hi 4.10.2.27. rd_pnf_3_lo 4.10.2.28. rd_pnf_3_hi 4.10.2.29. rd_pnf_4_lo 4.10.2.30. rd_pnf_4_hi 4.10.2.31. rd_pnf_5_lo 4.10.2.32. rd_pnf_5_hi 4.10.2.33. rd_pnf_6_lo 4.10.2.34. rd_pnf_6_hi 4.10.2.35. rd_pnf_7_lo 4.10.2.36. rd_pnf_7_hi 4.10.2.37. rd_pnf_8_lo 4.10.2.38. rd_pnf_8_hi 4.10.2.39. rd_pnf_9_lo 4.10.2.40. rd_pnf_9_hi 4.10.2.41. rd_pnf_10_lo 4.10.2.42. rd_pnf_10_hi 4.10.2.43. rd_pnf_11_lo 4.10.2.44. rd_pnf_11_hi 4.10.2.45. rd_pnf_12_lo 4.10.2.46. rd_pnf_12_hi 4.10.2.47. rd_pnf_13_lo 4.10.2.48. rd_pnf_13_hi 4.10.2.49. rd_pnf_14_lo 4.10.2.50. rd_pnf_14_hi 4.10.2.51. rd_pnf_15_lo 4.10.2.52. rd_pnf_15_hi 4.10.2.53. rd_pnf_16_lo 4.10.2.54. rd_pnf_16_hi 4.10.2.55. rd_pnf_17_lo 4.10.2.56. rd_pnf_17_hi 4.10.2.57. rd_pnf_18_lo 4.10.2.58. rd_pnf_18_hi 4.10.2.59. rd_pnf_19_lo 4.10.2.60. rd_pnf_19_hi 4.10.2.61. ter_dq_mask_0_lo 4.10.2.62. ter_dq_mask_0_hi 4.10.2.63. ter_dq_mask_1_lo 4.10.2.64. ter_dq_mask_1_hi 4.10.2.65. ter_lo 4.10.2.66. ter_hi
5. Test Engine IP - Software x
5.1. Overview 5.2. Python library 5.3. User programs 5.4. System Console library
5.2. Python library x
5.2.1. CSR AXI4-Lite Driver APIs 5.2.2. Memory AXI4 Driver APIs 5.2.3. General compiler APIs
5.2.1. CSR AXI4-Lite Driver APIs x
5.2.1.1. read_cmd 5.2.1.2. write_cmd
5.2.2. Memory AXI4 Driver APIs x
5.2.2.1. dq_alu_echo_op 5.2.2.2. dq_alu_invert_op 5.2.2.3. dq_alu_rotate_op 5.2.2.4. dq_alu_prbs_op 5.2.2.5. data_eq_dq_op 5.2.2.6. data_eq_raw_op 5.2.2.7. data_eq_addr_op 5.2.2.8. data_eq_id_op 5.2.2.9. dm_alu_echo_op 5.2.2.10. dm_alu_invert_op 5.2.2.11. dm_alu_rotate_op 5.2.2.12. dm_alu_prbs_op 5.2.2.13. strb_eq_dm_op 5.2.2.14. strb_eq_raw_op 5.2.2.15. addr_alu_echo_op 5.2.2.16. addr_alu_incr_op 5.2.2.17. addr_alu_rand_op 5.2.2.18. addr_op 5.2.2.19. write_worker_op 5.2.2.20. read_worker_op 5.2.2.21. write_cmd 5.2.2.22. read_cmd 5.2.2.23. wait_writes_cmd 5.2.2.24. wait_reads_cmd 5.2.2.25. sleep_cmd 5.2.2.26. driver_post_cmd 5.2.2.27. driver_wait_cmd 5.2.2.28. parallel_cmd 5.2.2.29. loop_cmd
5.2.3. General compiler APIs x
5.2.3.1. get_drivers 5.2.3.2. attach 5.2.3.3. dump
5.3. User programs x
5.3.1. Programs for Memory AXI4 Driver 5.3.2. Programs for CSR AXI4-Lite Driver
5.3.1. Programs for Memory AXI4 Driver x
5.3.1.1. Basic tutorials 5.3.1.2. Advanced tutorials 5.3.1.3. EMIF traffic patterns (for IO96B architecture) 5.3.1.4. HBM2E traffic patterns 5.3.1.5. MemSS traffic patterns (for IO96A architecture) 5.3.1.6. gencmd
5.3.1.1. Basic tutorials x
5.3.1.1.1. tut1_block_rw 5.3.1.1.2. tut2_byteen_test 5.3.1.1.3. tut3_instr_resume 5.3.1.1.4. tut4_parallel_rw 5.3.1.1.5. tut5_multi_id 5.3.1.1.6. tut6_custom_bw 5.3.1.1.7. tut7_driver_sync
5.3.1.2. Advanced tutorials x
5.3.1.2.1. adv1_basic_rw 5.3.1.2.2. adv2_addr_fields 5.3.1.2.3. adv3_instr_resume
5.3.1.3. EMIF traffic patterns (for IO96B architecture) x
5.3.1.3.1. emif_tg_emulation 5.3.1.3.2. emif_tg_emulation_lite 5.3.1.3.3. emif_tg_emulation_long 5.3.1.3.4. emif_tg_emulation_inf 5.3.1.3.5. emif_narrow_transfer
5.3.1.4. HBM2E traffic patterns x
5.3.1.4.1. hbm_simulation1 5.3.1.4.2. hbm_simulation
5.3.1.5. MemSS traffic patterns (for IO96A architecture) x
5.3.1.5.1. memss_default
5.3.2. Programs for CSR AXI4-Lite Driver x
5.3.2.1. HBM2E traffic patterns 5.3.2.2. MemSS traffic patterns (for IO96A architecture)
5.3.2.1. HBM2E traffic patterns x
5.3.2.1.1. hbm_simulation1
5.3.2.2. MemSS traffic patterns (for IO96A architecture) x
5.3.2.2.1. memss_default
5.4. System Console library x
5.4.1. testengine_num_drivers 5.4.2. testengine_driver_list 5.4.3. testengine_run 5.4.4. testengine_reset 5.4.5. testengine_get_errors 5.4.6. testengine_get_done 5.4.7. testengine_status 5.4.8. testengine_reprogram 5.4.9. testengine_axi4_parse_errors
1. About the Test Engine FPGA IP
2. Test Engine IP - Introduction
3. Parameterizing the Test Engine IP
4. Test Engine IP - Interface Signals
5. Test Engine IP - Software
6. Test Engine IP - Limitations
7. Document Revision History for the Test Engine FPGA IP User Guide

4.5. Memory AXI4 Driver Interface Signals

Table 17.  Clocks and Resets Signals
Port Name Width Direction Description
driver#_clk 1 Input Clock Input for the Memory AXI4 Driver. This is the clock that will be used for the AXI4 interface.
driver#_reset_n 1 Input Reset Input for the Memory AXI4 Driver. Asserting this reset will reset the traffic generation logic and the CSR registers.
driver#_csr_clk 1 Input Clock Input for the Memory AXI4 Driver sideband interface.
driver#_csr_reset_n 1 Input Reset Input for the Memory AXI4 Driver sideband interface. Asserting this reset will only cause the sideband interface to ignore any requests. This will not reset the CSR registers to default values.
Note: For the driver#_* ports, # is the driver index.
Table 18.  AXI4 Manager Signals
Port Name Width Direction description
driver#_axi4_awready 1 Input Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_axi4_awvalid 1 Output Write Address Channel Valid. This signal indicates that valid write address and control information are available.
driver#_axi4_awid 1-18 Output Write address channel command ID tag. The width of this signal is determined by the Write ID Width parameter.
driver#_axi4_awaddr 1-64 Output Write address. The write address gives the address of the first transfer in a write burst transaction. The width is tied to the value of the Write Address width parameter.
driver#_axi4_awlen 8 Output Write Burst Length. The burst length gives the exact number of transfers in an AXI burst.
driver#_axi4_awsize 3 Output Write Burst Size. This signal indicates the number of AXI byte lanes containing valid data in each transfer of the burst.
driver#_axi4_awburst 2 Output Write Burst type. The burst type and length determine how the address for each transfer within the burst is calculated.
driver#_axi4_awlock 1 Output Write Lock Type. Provides additional information about the atomic characteristics of the transfer.
driver#_axi4_awcache 4 Output Write Memory type. This signal indicates how transactions are required to progress through a system. This is an optional port controlled by the Use AWCACHE parameter.
driver#_axi4_awprot 3 Output Write Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. This is controlled by the Use AWPROT parameter.
driver#_axi4_awqos 4 Output Write Quality-of-service identifier for this write command. This signal is optional on the interface and determined by the Use AWQOS parameter.
driver#_axi4_awregion 4 Output

Write Region identifier. Permits a single physical interface on a subordinate to be used for multiple logical interfaces. Optional port on the interface controlled by Use AWREGION parameter.

driver#_axi4_awuser 1-64 Output Optional User-defined signal in the write address channel. Width will match the AWUSER parameter.
driver#_axi4_arready 1 Input Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_axi4_arvalid 1 Output Read Address Valid. This signal indicates that valid read address and control information are available.
driver#_axi4_arid 1-18 Output Read address channel command ID tag. Controlled by the Read ID width parameter.
driver#_axi4_araddr 1-64 Output Read Address. The read address gives the address of the first transfer in a read burst transaction. Controlled by Read Address Width Parameter and should have the same width range.
driver#_axi4_arlen 8 Output Read Burst Length. The burst length gives the exact number of transfers in an AXI burst.
driver#_axi4_arsize 3 Output Read Burst Size. This signal indicates the number of AXI byte lanes containing valid data in each transfer of the burst.
driver#_axi4_arburst 2 Output Read Burst type. The burst type and length determine how the address for each transfer within the burst is calculated.
driver#_axi4_arlock 1 Output Read Lock type. This signal provides additional information about the atomic characteristics of the transfer. Optional signal on the interface exposed by Use ARLOCK.
driver#_axi4_arcache 4 Output Read Memory type. This signal indicates how transactions are required to progress through a system. This is an optional port controlled by the Use ARCACHE parameter.
driver#_axi4_arprot 3 Output Read Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access. Optional signal on the interface set by the Use ARPROT parameter.
driver#_axi4_arqos 4 Output Quality-of-service identifier for this read command. This signal is optional and dependent on the Use ARQOS parameter.
driver#_axi4_arregion 4 Output Region identifier. Permits a single physical interface on a subordinate to be used for multiple logical interfaces Optional signal exposed if Use ARREGION parameter is set.
driver#_axi4_aruser 1-64 Output User signal. Optional User-defined signal in the read address channel. Optional signal controlled by Use ARUSER with width defined by the ARUSER width parameter.
driver#_axi4_wready 1 Input Write Data Channel Ready. This signal indicates that the subordinate can accept the write data.
driver#_axi4_wvalid 1 Output Write Data Channel Valid. This signal indicates that valid write data and strobes are available.
driver#_axi4_wdata 8, 16, 32, 64, 128, 256, 512, 1024 Output Write Data. The port width is equal to 2^N where N is a positive integer between 3 and 10, where N is equal to the floor of log2 of the Write Data Width parameter.
driver#_axi4_wuser 1-64 Output User signal. Optional User-defined signal in the write data channel. Value is determined by the Write Data width parameter. If this value is 0 this port is not added to the interface.
driver#_axi4_wstrb 1, 2, 4, 8, 16, 32, 64, 128 Output Write Strobes (Byte Enables). The width of the wstrb port is equal to wdata port divided by 8.
driver#_axi4_wlast 1 Output Write Last. This signal indicates the last transfer in a write burst.
driver#_axi4_bready 1 Output Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_axi4_bvalid 1 Input Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_axi4_bid 9 Input Response ID Tag. This signal is the ID tag of the write response, and matches the ID tag of the command for which this is the response. Controlled by Write ID width parameter.
driver#_axi4_buser 1-64 Input User signal. Optional User-defined signal in the write response channel. Optional signal on the interface controlled by Use BUSER and BUSER width Parameters.
driver#_axi4_bresp 2 Input Write Response. This signal indicates the result of the Write command.
driver#_axi4_rready 1 Output Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.
driver#_axi4_rvalid 1 Input Read Valid. This signal indicates that a valid read response is available.
driver#_axi4_rid 1-18 Input Read address channel command ID tag. The width of this signal is determined by the Write ID Width parameter.
driver#_axi4_rdata 8, 16, 32, 64, 128, 256, 512, 1024 Input Read Data. The port width is equal to 2^N where N is a positive integer between 3 and 10, where N is equal to the floor of log2 of the Read Data Width parameter.
driver#_axi4_ruser 1-64 Input Read User signal. Optional User-defined signal in the read data channel. Value is determined by Read Data width parameter - Read data width. If this value is 0 this port is not added to the interface.
driver#_axi4_rresp 2 Input Read response. This signal indicates the status of the read transfer.
driver#_axi4_rlast 1 Input Read Last. This signal indicates the last transfer in a read burst.
Note: For the driver#_* ports, # is the driver index.
Table 19.  Sideband AXI4-Lite Signals
Port Name Width Direction Description
driver#_csr_axi4l_awaddr 24 Input Write address.
driver#_csr_axi4l_awvalid 1 Input Write Address Channel Valid. This signal indicates that valid write address and control information are available.
driver#_csr_axi4l_awready 1 Output Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_awprot 3 Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_araddr 24 Input Read address.
driver#_csr_axi4l_arvalid 1 Input Read Address Valid. This signal indicates that valid read address and control information are available.
driver#_csr_axi4l_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_arprot 3 Input Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_wdata 32 Input Write data.
driver#_csr_axi4l_wstrb 4 Input Write Strobes (Byte Enables).
driver#_csr_axi4l_wvalid 1 Input Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_wready 1 Output Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_bresp 2 Output Write Response. This signal indicates the result of the Write command.
driver#_csr_axi4l_bvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_bready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_rdata 32 Output Read data.
driver#_csr_axi4l_rresp 2 Output Read response. This signal indicates the status of the read transfer.
driver#_csr_axi4l_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available
driver#_csr_axi4l_rready 1 Input Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information
Note: For the driver#_* ports, # is the driver index.
The Sideband CSR ports are available only when the Remote Access > Configuration Interface parameter is set to Export.
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