Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.8. Memory Reset Driver Interface Signals

Table 26.  Clock and Reset Signals
Port Name Width Direction Description
driver#_clk 1 Input Clock Input for the Memory Reset Driver. This is the clock that will be used for the reset interface.
driver#_reset_n 1 Input Reset Input for the Memory Reset Driver. Asserting this reset will reset the traffic generation logic and the CSR registers.
driver#_csr_clk 1 Input Clock Input for the Memory Reset Driver sideband interface.
driver#_csr_reset_n 1 Input Reset Input for the Memory Reset Driver sideband interface.
Note: For the driver#_* ports, # is the driver index.
Table 27.  Memory Subsystem Reset Conduit Signals
Port Name Width Direction Description
driver#_app_ss_rst_req 1 Output Signal from user logic to request the memory interface to be reset and recalibrated. Active high synchronous signal. Synchronized to the app_ss_mem_usr_clk clock.
driver#_ss_app_rst_rdy 1 Input Signal from memory interface to indicate whether it has completed a reset sequence, is currently out of reset, and is ready for a new reset request. Active high synchronous signal. Synchronized to the app_ss_mem_usr_clk clock
driver#_app_ss_cold_rst_n 1 Output Resets the functionality of the memory subsystem. Resets all sticky bits. This signal is active-LOW. Applicable when memory subsystem has sticky bits.
driver#_ss_app_cold_rst_ack_n 1 Input Reset handshake. On of the use case is to serve as feedback that the reset is already effectuated when the corresponding reset is implemented as synchronous reset
Note: For the driver#_* ports, # is the driver index.
Table 28.  Sideband AXI4-Lite Signals
Port Name Width Direction Description
driver#_csr_axi4l_awaddr 22 Input Write address.
driver#_csr_axi4l_awvalid 1 Input Write Address Channel Valid. This signal indicates that valid write address and control information are available.
driver#_csr_axi4l_awready 1 Output Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_awprot 3 Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_araddr 22 Input Read address.
driver#_csr_axi4l_arvalid 1 Input Read Address Valid. This signal indicates that valid read address and control information are available.
driver#_csr_axi4l_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_arprot 3 Input Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_wdata 32 Input Write data.
driver#_csr_axi4l_wstrb 4 Input Write Strobes (Byte Enables).
driver#_csr_axi4l_wvalid 1 Input Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_wready 1 Output Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_bresp 2 Output Write Response. This signal indicates the result of the Write command.
driver#_csr_axi4l_bvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_bready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_rdata 32 Output Read data.
driver#_csr_axi4l_rresp 2 Output Read response. This signal indicates the status of the read transfer.
driver#_csr_axi4l_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available.
driver#_csr_axi4l_rready 1 Input Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.
Note: For the driver#_* ports, # is the driver index.

The Sideband CSR ports are available only when the Remote Access > Configuration Interface parameter is set to Export.