Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.10. Registers

To access the control and status registers (CSR), you must set the Remote Access > Configuration Interface parameter in the Test Engine IP to Export or to Remote Access via JTAG.

If you set Configuration Interface to Export, the Global CSR and each driver will have their own individual sideband AXI-Lite bus. When setting address maps for these ports, provide a minimum address range of 0x0100_0000 for full access to the CSR space.

If you set Configuration Interface to Remote Access via JTAG, access to the CSR is available through a JTAG interface accessible through System Console. For this interface, the base address for each module in the Test Engine is assigned automatically with address offsets of 0x0100_0000, starting with the Global CSR, then each driver in order. Thus the base addresses have the following pattern:

  • Global CSR: 0x0000_0000
  • Driver 0: 0x0100_0000
  • Driver 1: 0x0200_0000
  • Driver 2: 0x0300_0000
Note: All CSR registers are 32 bits wide.