Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.6. CSR AXI-Lite Driver Interface Signals

Table 20.  Clock and Reset Signals
Port Name Width Direction Description
driver#_clk 1 Input Clock Input for the CSR AXI4-Lite Driver. This is the clock that will be used for the AXI4-Lite interface.
driver#_reset_n 1 Input Reset Input for the Memory AXI4 Driver. Asserting this reset will reset the traffic generation logic and the CSR registers.
driver#_csr_clk 1 Input Clock Input for the CSR AXI4-Lite Driver sideband interface.
driver#_csr_reset_n 1 Input Reset Input for the CSR AXI4-Lite Driver sideband interface.
Note: For the driver#_* ports, # is the driver index.
Table 21.  AXI4-Lite Manager Signals
Port Name Width Direction Description
driver#_axi4l_awaddr 1-64 Output Write Address. The width is tied to the value of the Write Address width parameter.
driver#_axi4l_awvalid 1 Output Write Address Channel Valid. This signal indicates that valid write address and control information are available.
driver#_axi4l_awready 1 Input Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_axi4l_awprot 3 Output Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access
driver#_axi4l_araddr 1-64 Output Read address. The width is tied to the value of the Read Address width parameter.
driver#_axi4l_arvalid 1 Output Read Address Valid. This signal indicates that valid read address and control information are available.
driver#_axi4l_arready 1 Input Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals
driver#_axi4l_arprot 3 Output Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_axi4l_wdata 32-64 Output Write Data. The width is tied to the value of the Write Data width parameter.
driver#_axi4l_wstrb 4 Output Write Strobes (Byte Enables).
driver#_axi4l_wvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_axi4l_wready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_axi4l_bresp 2 Input Write Response. This signal indicates the result of the Write command.
driver#_axi4l_bvalid 1 Input Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_axi4l_bready 1 Output Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_axi4l_rdata 32-64 Input Read data. The width is tied to the value of the Read Data width parameter.
driver#_axi4l_rresp 2 Input Read response. This signal indicates the status of the read transfer.
driver#_axi4l_rvalid 1 Input Read Valid. This signal indicates that a valid read response is available.
driver#_axi4l_rready 1 Output Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.
Note: For the driver#_* ports, # is the driver index.
Table 22.  Sideband AXI4-Lite Signals
Port Name Width Direction Description
driver#_csr_axi4l_awaddr 22 Input Write address.
driver#_csr_axi4l_awvalid 1 Input Write Address Channel Valid. This signal indicates that valid write address and control information are available.
driver#_csr_axi4l_awready 1 Output Write Address Channel Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_awprot 3 Input Protection type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_araddr 22 Input Read address
driver#_csr_axi4l_arvalid 1 Input Read Address Valid. This signal indicates that valid read address and control information are available.
driver#_csr_axi4l_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
driver#_csr_axi4l_arprot 3 Input Protection Type. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.
driver#_csr_axi4l_wdata 32 Input Write data.
driver#_csr_axi4l_wstrb 4 Input Write Strobes (Byte Enables).
driver#_csr_axi4l_wvalid 1 Input Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_wready 1 Output Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_bresp 2 Output Write Response. This signal indicates the result of the Write command.
driver#_csr_axi4l_bvalid 1 Output Write Response Channel Valid. This signal indicates that a valid write response is available.
driver#_csr_axi4l_bready 1 Input Write Response Channel Ready. This signal indicates that the manager can accept a write response.
driver#_csr_axi4l_rdata 32 Output Read data.
driver#_csr_axi4l_rresp 2 Output Read response. This signal indicates the status of the read transfer.
driver#_csr_axi4l_rvalid 1 Output Read Valid. This signal indicates that a valid read response is available
driver#_csr_axi4l_rready 1 Input Read Response Channel Ready. This signal indicates that the manager can accept the read data and response information.
Note: For the driver#_* ports, # is the driver index.

The Sideband CSR ports are available only when the Remote Access > Configuration Interface parameter is set to Export.