Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.10.2.19. rd_err_counters_1_lo

Table 65.  address=0x00A8
Field Bits Access Default Description
num_rdata_errors [31:0] Read 0 Number of RDATA mismatches.