Test Engine FPGA IP User Guide: Agilex™ 5 and Agilex™ 7 FPGAs

ID 817758
Date 7/08/2024
Public
Document Table of Contents

4.10.1.7. driver_run_bitmask_2

Table 36.  address=0x0088
Field Bits Access Default Description
driver_run_bitmask [31:0] Read/Write 0 Set/Clear each bit to run/stop each corresponding driver [95:64].