GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
ID
817660
Date
4/07/2025
Public
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1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
3.1. IP Overview
3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP
3.4. Reconfigurable PHY
3.5. Signal and Port Reference
3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath
3.7. Clocking
3.8. Custom Cadence Generation Ports and Logic
3.9. Asserting Reset
3.10. Bonding Implementation
3.11. Configuration Register
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing
3.13. Configurable Quartus® Prime Software Settings
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. Preset IP Parameter Settings
3.3.2. Mode and Common Datapath Options
3.3.3. Reconfigurable PHY Settings
3.3.4. TX Datapath Options
3.3.5. RX Datapath Options
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations
3.3.7. FEC Options
3.3.8. PCS Options
3.3.9. Avalon® Memory-Mapped Interface Options
3.3.10. Register Map IP-XACT Support
3.3.11. Analog Parameter Options
3.5.1. TX and RX Parallel and Serial Interface Signals
3.5.2. TX and RX Reference Clock and Clock Output Interface Signals
3.5.3. Reset Signals
3.5.4. FEC Signals
3.5.5. Custom Cadence Control and Status Signals
3.5.6. RX PMA Status Signals
3.5.7. TX and RX PMA and Core Interface FIFO Signals
3.5.8. Avalon Memory-Mapped Interface Signals
3.9.1. Reset Signal Requirements
3.9.2. Power On Reset Requirements
3.9.3. Reset Signals—Block Level
3.9.4. Run-time Reset Sequence—TX
3.9.5. Run-time Reset Sequence—RX
3.9.6. Run-time Reset Sequence—TX + RX
3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery)
3.9.8. TX PLL Lock Loss
3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
5.1. IP Requirements
5.2. IP Parameters
5.3. IP Port List
5.4. GTS Reset Sequencer Intel FPGA IP General Interface
5.5. GTS Reset Sequencer Intel FPGA IP Design Flow
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench
6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design
6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description
6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench
6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench
Follow these steps to simulate the testbench:
Figure 96. Steps to Simulate the Example Design
- At the command prompt, change to the testbench simulation directory <example_design/testbench>.
cd <directphy_example_design>/example_design/testbench
- Run the simulation using the supported simulators by executing the simulation script file. To simulate with VCS* MX, change to the example_design/testbench directory and launch the simulation using the shell script:
sh run_vcsmx.sh
Note: For VCS* MX simulations, the simulator generates a synopsys/vcsmx folder upon a successful simulation run. You have to generate the simulation waveform from the synopsys/vcsmx folder.To run the simulation in QuestaSim* , run the following command:vsim -c -do run_vsim.tcl
To run the simulation in Xcelium* , run the following command:sh run_xcelium.sh
To run the simulation in Riviera-PRO* , run the following command:vsim -c -do run_rivierasim.do
Note: Currently only Riviera-PRO* version 2024.04 is supported. - The following steps show the simulation testbench flow for the Reconfigurable PHY example design:
- Wait for the DR controller bring up:
- Wait for the DR controller to be ready either by ensuring o_in_progress = 0 or poll stat.ready (0x70[0]) until it is 1’b1.
- For Base profile simulation:
- Assert the resets, tx_reset and rx_reset to reset the IP.
- Wait until resets are acknowledged, tx_reset_ack and rx_reset_ack go high.
- Deassert the resets, tx_reset and rx_reset.
- Monitor tx_ready bit is set to 1, indicating the TX path is ready.
- Monitor rx_ready bit is set to 1, indicating the RX path is ready.
- Monitor tx_pll_locked bit is set to 1, indicating TX PLL is locked to the reference clock within the PPM threshold status signal.
- Monitor rx_is_lockedtoref bit is set to 1, indicating the CDR is frequency locked to reference clock within the PPM threshold.
- Monitor rx_is_lockedtodata bit is set to 1, indicating that the CDR is in locked-to-data mode.
- Monitor tx_clkout_freq_valid bit is set to 1, indicating TX clock out frequency is within the upper and lower limits as expected in the definition file.
- Monitor rx_clkout_freq_valid bit is set to 1, indicating RX clock out frequency is within the upper and lower limits as expected in the definition file.
- Monitor verifier_lock bit is set to 1, indicating a lock to the RX data pattern after successfully predicting 16 consecutive patterns in RX data.
- Monitor verifier_error bit is not set to 1. If 1, this indicates the RX data is different than the expected result.
- To switch profiles:
- Assert the resets, tx_reset and rx_reset to reset the IP.
- Wait until resets are acknowledged, tx_reset_ack and rx_reset_ack go high.
- Configure the current profile ID and target profile ID. For example, the current profile ID is 0x1 and the target profile ID is 0x2:
- Program the current profile to disable:
- next_id_cfg[0].next_id_lo (0x00[14:0]) = 0x1 (current profile)
- next_id_cfg[0].next_id_lo_act (0x00[15]) = 0x0 (neutral)
- Program the target profiles to enable:
- next_id_cfg[0].next_id_hi (0x00[30:16]) = 0x2 (target profile)
- next_id_cfg[0].next_id_hi_act (0x00[31]) = 0x1 (active)
- Program the current profile to disable:
- Select the mode and trigger DR to start dynamic reconfiguration:
- Poll trigger.trigger (0x50[0]) until it is 1’b0.
- Wait for DR to be completed either by ensuring o_in_progress = 0 or poll stat.ready (0x70[0]) until it is 1’b1.
- For Secondary profile simulation:
- Program protocol IPs soft CSRs if required.
- Wait until resets are acknowledged, tx_reset_ack and rx_reset_ack go high.
- Deassert the resets, tx_reset and rx_reset.
- Monitor tx_ready bit is set to 1, indicating the TX path is ready.
- Monitor rx_ready bit is set to 1, indicating the RX path is ready.
- Monitor tx_pll_locked bit is set to 1, indicating TX PLL is locked to the reference clock within the PPM threshold status signal.
- Monitor rx_is_lockedtoref bit is set to 1, indicating CDR is frequency locked to reference clock within the PPM threshold.
- Monitor rx_is_lockedtodata bit is set to 1, indicating indicates that the CDR is in locked-to-data mode.
- Monitor tx_clkout_freq_valid bit is set to 1, indicating TX clock out frequency is within the upper and lower limits as expected in the definition file.
- Monitor rx_clkout_freq_valid bit is set to 1, indicating RX clock out frequency is within the upper and lower limits as expected in the definition file.
- Monitor verifier_lock bit is set to 1, indicating a lock to the RX data pattern after successfully predicting 16 consecutive patterns in RX data.
- Monitor verifier_error bit is not set to 1. If 1, this indicates the RX data is different than the expected result.
- Wait for the DR controller bring up:
- To switch profiles use step 3. and repeat step 4.
- Analyze the results, a passing testbench displays the following messages in the simulation window, Test case Passed and Simulation Passed, as shown in the following figure.
Figure 97. Sample Results for the Reconfigurable PHY Example Design Testbench