GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

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ID 817660
Date 4/07/2025
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Document Table of Contents
Document Table of Contents x
1. GTS Transceiver Overview 2. GTS Transceiver Architecture 3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP 4. Implementing the GTS System PLL Clocks Intel FPGA IP 5. Implementing the GTS Reset Sequencer Intel FPGA IP 6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 7. Design Assistance Tools 8. Debugging GTS Transceiver Links with Transceiver Toolkit 9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
1. GTS Transceiver Overview x
1.1. GTS Transceiver Design Flow
2. GTS Transceiver Architecture x
2.1. Building Blocks 2.2. Channel Placement Rules and Design Requirements 2.3. PMA Architecture 2.4. PCS Architecture 2.5. Forward Error Correction (FEC) Architecture 2.6. Clock Architecture 2.7. Bonding and Deskew
2.1. Building Blocks x
2.1.1. PMA 2.1.2. FEC 2.1.3. PCS 2.1.4. Ethernet MAC 2.1.5. PCI Express* Hard IP 2.1.6. PLL and Clock Networks 2.1.7. Avalon® Memory-Mapped Interface
2.1.1. PMA x
2.1.1.1. Protocol Support Using PMA Direct Mode
2.1.1.1. Protocol Support Using PMA Direct Mode x
2.1.1.1.1. SDI 2.1.1.1.2. HDMI 2.1.1.1.3. CPRI 2.1.1.1.4. GPON
2.2. Channel Placement Rules and Design Requirements x
2.2.1. Hard IP Rules 2.2.2. Use Scenario Rules 2.2.3. Unused PMA Rules 2.2.4. General Design Requirement
2.2.3. Unused PMA Rules x
2.2.3.1. Unused PMA Not Planned for Use in the Future 2.2.3.2. Unused PMA Planned for Use in the Future
2.3. PMA Architecture x
2.3.1. Transmitter PMA Architecture 2.3.2. Receiver PMA Architecture 2.3.3. PMA Loopback Modes
2.3.1. Transmitter PMA Architecture x
2.3.1.1. Transmitter Buffer 2.3.1.2. Serializer 2.3.1.3. Data Pattern Generator and Verifier
2.3.2. Receiver PMA Architecture x
2.3.2.1. Receiver Buffer and Equalizer 2.3.2.2. Deserializer 2.3.2.3. CDR Block 2.3.2.4. PMA Tuning
2.3.2.1. Receiver Buffer and Equalizer x
2.3.2.1.1. Control Unit
2.5. Forward Error Correction (FEC) Architecture x
2.5.1. FEC Loopback Mode
2.6. Clock Architecture x
2.6.1. Reference Clock Network 2.6.2. Datapath Clock Network 2.6.3. System PLL 2.6.4. Datapath Clock Cadences 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and HVIO Bank
2.6.1. Reference Clock Network x
2.6.1.1. Single GTS Transceiver Bank Device 2.6.1.2. PMA Primary PLL Configuration
2.6.3. System PLL x
2.6.3.1. I/O PLLs in HVIO Bank as System PLL 2.6.3.2. Running PCIe* and Non- PCIe* Protocols in a GTS Transceiver Bank 2.6.3.3. System PLL Clock for FPGA Core 2.6.3.4. System PLL with HVIO Reference Clock
2.7. Bonding and Deskew x
2.7.1. Bonding Architecture 2.7.2. TX Deskew Function
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.1. IP Overview 3.2. Designing with the GTS PMA/FEC Direct PHY Intel FPGA IP 3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP 3.4. Reconfigurable PHY 3.5. Signal and Port Reference 3.6. Bit Mapping for PMA, FEC, and PCS Mode PHY TX and RX Datapath 3.7. Clocking 3.8. Custom Cadence Generation Ports and Logic 3.9. Asserting Reset 3.10. Bonding Implementation 3.11. Configuration Register 3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing 3.13. Configurable Quartus® Prime Software Settings 3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.1. IP Overview x
3.1.1. PMA Direct Supported Modes 3.1.2. FEC Direct Supported Modes 3.1.3. PCS Direct Supported Modes 3.1.4. Unsupported PMA/FEC/PCS Modes
3.3. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.3.1. Preset IP Parameter Settings 3.3.2. Mode and Common Datapath Options 3.3.3. Reconfigurable PHY Settings 3.3.4. TX Datapath Options 3.3.5. RX Datapath Options 3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations 3.3.7. FEC Options 3.3.8. PCS Options 3.3.9. Avalon® Memory-Mapped Interface Options 3.3.10. Register Map IP-XACT Support 3.3.11. Analog Parameter Options
3.3.4. TX Datapath Options x
3.3.4.1. TX PMA Interface Parameters
3.3.5. RX Datapath Options x
3.3.5.1. RX PMA Interface Parameters
3.3.6. PMA Configuration Rules for Specific Protocol Mode Implementations x
3.3.6.1. PMA Configuration Rules for SDI Mode 3.3.6.2. PMA Configuration Rules for HDMI Mode 3.3.6.3. PMA Configuration Rules for CPRI Mode 3.3.6.4. PMA Configuration Rules for GPON Mode
3.4. Reconfigurable PHY x
3.4.1. Clock Generation and Constraints for Multiple Profiles Design
3.5. Signal and Port Reference x
3.5.1. TX and RX Parallel and Serial Interface Signals 3.5.2. TX and RX Reference Clock and Clock Output Interface Signals 3.5.3. Reset Signals 3.5.4. FEC Signals 3.5.5. Custom Cadence Control and Status Signals 3.5.6. RX PMA Status Signals 3.5.7. TX and RX PMA and Core Interface FIFO Signals 3.5.8. Avalon Memory-Mapped Interface Signals
3.7. Clocking x
3.7.1. Clock Ports 3.7.2. Recommended tx/rx_coreclkin Connection and tx/rx_clkout2 Source 3.7.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2 3.7.4. PMA Fractional Mode 3.7.5. Input Reference Clock Buffer Protection
3.7.5. Input Reference Clock Buffer Protection x
3.7.5.1. Reference Clock Buffer Register Information 3.7.5.2. Re-enabling the Reference Clock Buffers
3.8. Custom Cadence Generation Ports and Logic x
3.8.1. Enabling the i_tx_cadence_slow_clk_locked Port
3.9. Asserting Reset x
3.9.1. Reset Signal Requirements 3.9.2. Power On Reset Requirements 3.9.3. Reset Signals—Block Level 3.9.4. Run-time Reset Sequence—TX 3.9.5. Run-time Reset Sequence—RX 3.9.6. Run-time Reset Sequence—TX + RX 3.9.7. RX Data Loss/CDR Lock Loss (Auto-Recovery) 3.9.8. TX PLL Lock Loss 3.9.9. TX PLL Lock Loss Auto-Recovery (Soft CSR Enabled)
3.10. Bonding Implementation x
3.10.1. Bonding Placement Requirements 3.10.2. Multilane RX Simplex Implementation
3.11. Configuration Register x
3.11.1. GTS PMA and FEC Direct PHY Soft CSR Register Map 3.11.2. GTS PMA Register Map 3.11.3. Accessing Configuration Registers 3.11.4. Configuration Registers for the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY
3.11.2. GTS PMA Register Map x
3.11.2.1. Logical Avalon® Memory-Mapped Port Indexing
3.11.3. Accessing Configuration Registers x
3.11.3.1. Accessing GTS PMA and FEC Direct PHY Soft CSR Registers 3.11.3.2. Accessing GTS PMA Registers
3.12. Configuring the GTS PMA/FEC Direct PHY Intel FPGA IP for Hardware Testing x
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP 3.12.2. Using JTAG to Avalon Master Bridge Intel FPGA IP
3.12.1. Using Debug Endpoint Interface within the GTS PMA/FEC Direct PHY Intel FPGA IP x
3.12.1.1. RTL Connection Example for Debug Endpoint Avalon® Interface
3.12.2. Using JTAG to Avalon Master Bridge Intel FPGA IP x
3.12.2.1. RTL Connection Example for JTAG to Avalon Master Bridge Intel® FPGA IP
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface x
3.14.1. Direct Register Method 3.14.2. GTS Attribute Access Method
3.14.1. Direct Register Method x
3.14.1.1. Direct Register Method Examples
3.14.2. GTS Attribute Access Method x
3.14.2.1. GTS Attribute Access Method Example 1 3.14.2.2. GTS Attribute Access Method Example 2 3.14.2.3. GTS Attribute Access Method Example 3
4. Implementing the GTS System PLL Clocks Intel FPGA IP x
4.1. IP Parameters 4.2. IP Port List 4.3. Mode of System PLL - System PLL Reference Clock and Output Frequencies 4.4. Guidelines for GTS System PLL Clocks Intel FPGA IP Usage 4.5. Guidelines to Indicate System PLL Reference Clock is Ready
4.5. Guidelines to Indicate System PLL Reference Clock is Ready x
4.5.1. Example Flow to Indicate System PLL Reference Clock is Ready
5. Implementing the GTS Reset Sequencer Intel FPGA IP x
5.1. IP Requirements 5.2. IP Parameters 5.3. IP Port List 5.4. GTS Reset Sequencer Intel FPGA IP General Interface 5.5. GTS Reset Sequencer Intel FPGA IP Design Flow 5.6. GTS Reset Sequencer Intel FPGA IP Use Cases 5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
5.6. GTS Reset Sequencer Intel FPGA IP Use Cases x
5.6.1. Example Use Case 1 5.6.2. Example Use Case 2
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.1. Instantiating the GTS PMA/FEC Direct PHY Intel FPGA IP 6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.3. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Functional Description 6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench 6.5. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.6. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design 6.7. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design 6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design 6.9. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Functional Description 6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench 6.11. Compiling the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design 6.12. Hardware Testing the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design
6.2. Generating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design x
6.2.1. Fast Simulation Support 6.2.2. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Directory Structure
6.4. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Example Design Testbench x
6.4.1. Modifying the Example Design and Performing Simulation
6.8. Generating the GTS PMA/FEC Direct PHY Intel® FPGA IP Reconfigurable Example Design x
6.8.1. Fast Simulation Support 6.8.2. GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Directory Structure
7. Design Assistance Tools x
7.1. Clocking and Datapath Tool 7.2. TX Equalizer Tool
8. Debugging GTS Transceiver Links with Transceiver Toolkit x
8.1. GTS Transceiver Toolkit Parameter Settings 8.2. GTS Transceiver Toolkit GUI 8.3. GTS Transceiver Debugging Flow Walkthrough
8.2. GTS Transceiver Toolkit GUI x
8.2.1. Collection View
8.3. GTS Transceiver Debugging Flow Walkthrough x
8.3.1. Modifying the Design to Enable GTS Transceiver Debug Toolkit 8.3.2. Programming the Design into an Intel FPGA 8.3.3. Loading the Design to the Transceiver Toolkit 8.3.4. Creating Transceiver Links 8.3.5. Running BER Tests 8.3.6. Running Eye Viewer Tests 8.3.7. Running Link Optimization Tests
1. GTS Transceiver Overview
2. GTS Transceiver Architecture
3. Implementing the GTS PMA/FEC Direct PHY Intel FPGA IP
4. Implementing the GTS System PLL Clocks Intel FPGA IP
5. Implementing the GTS Reset Sequencer Intel FPGA IP
6. GTS PMA/FEC Direct PHY Intel FPGA IP Example Design
7. Design Assistance Tools
8. Debugging GTS Transceiver Links with Transceiver Toolkit
9. Document Revision History for the GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs

6.10. Simulating the GTS PMA/FEC Direct PHY Intel FPGA IP Reconfigurable PHY Example Design Testbench

Follow these steps to simulate the testbench:
Figure 96. Steps to Simulate the Example Design
  1. At the command prompt, change to the testbench simulation directory <example_design/testbench>.
    cd <directphy_example_design>/example_design/testbench
  2. Run the simulation using the supported simulators by executing the simulation script file. To simulate with VCS* MX, change to the example_design/testbench directory and launch the simulation using the shell script:
    sh run_vcsmx.sh
    Note: For VCS* MX simulations, the simulator generates a synopsys/vcsmx folder upon a successful simulation run. You have to generate the simulation waveform from the synopsys/vcsmx folder.
    To run the simulation in QuestaSim* , run the following command:
    vsim -c -do run_vsim.tcl
    To run the simulation in Xcelium* , run the following command:
    sh run_xcelium.sh
    To run the simulation in Riviera-PRO* , run the following command:
    vsim -c -do run_rivierasim.do
    Note: Currently only Riviera-PRO* version 2024.04 is supported.
  3. The following steps show the simulation testbench flow for the Reconfigurable PHY example design:
    1. Wait for the DR controller bring up:
      1. Wait for the DR controller to be ready either by ensuring o_in_progress = 0 or poll stat.ready (0x70[0]) until it is 1’b1.
    2. For Base profile simulation:
      1. Assert the resets, tx_reset and rx_reset to reset the IP.
      2. Wait until resets are acknowledged, tx_reset_ack and rx_reset_ack go high.
      3. Deassert the resets, tx_reset and rx_reset.
      4. Monitor tx_ready bit is set to 1, indicating the TX path is ready.
      5. Monitor rx_ready bit is set to 1, indicating the RX path is ready.
      6. Monitor tx_pll_locked bit is set to 1, indicating TX PLL is locked to the reference clock within the PPM threshold status signal.
      7. Monitor rx_is_lockedtoref bit is set to 1, indicating the CDR is frequency locked to reference clock within the PPM threshold.
      8. Monitor rx_is_lockedtodata bit is set to 1, indicating that the CDR is in locked-to-data mode.
      9. Monitor tx_clkout_freq_valid bit is set to 1, indicating TX clock out frequency is within the upper and lower limits as expected in the definition file.
      10. Monitor rx_clkout_freq_valid bit is set to 1, indicating RX clock out frequency is within the upper and lower limits as expected in the definition file.
      11. Monitor verifier_lock bit is set to 1, indicating a lock to the RX data pattern after successfully predicting 16 consecutive patterns in RX data.
      12. Monitor verifier_error bit is not set to 1. If 1, this indicates the RX data is different than the expected result.
    3. To switch profiles:
      1. Assert the resets, tx_reset and rx_reset to reset the IP.
      2. Wait until resets are acknowledged, tx_reset_ack and rx_reset_ack go high.
      3. Configure the current profile ID and target profile ID. For example, the current profile ID is 0x1 and the target profile ID is 0x2:
        • Program the current profile to disable:
          1. next_id_cfg[0].next_id_lo (0x00[14:0]) = 0x1 (current profile)
          2. next_id_cfg[0].next_id_lo_act (0x00[15]) = 0x0 (neutral)
        • Program the target profiles to enable:
          1. next_id_cfg[0].next_id_hi (0x00[30:16]) = 0x2 (target profile)
          2. next_id_cfg[0].next_id_hi_act (0x00[31]) = 0x1 (active)
      4. Select the mode and trigger DR to start dynamic reconfiguration:
        1. Poll trigger.trigger (0x50[0]) until it is 1’b0.
        2. Wait for DR to be completed either by ensuring o_in_progress = 0 or poll stat.ready (0x70[0]) until it is 1’b1.
    4. For Secondary profile simulation:
      1. Program protocol IPs soft CSRs if required.
      2. Wait until resets are acknowledged, tx_reset_ack and rx_reset_ack go high.
      3. Deassert the resets, tx_reset and rx_reset.
      4. Monitor tx_ready bit is set to 1, indicating the TX path is ready.
      5. Monitor rx_ready bit is set to 1, indicating the RX path is ready.
      6. Monitor tx_pll_locked bit is set to 1, indicating TX PLL is locked to the reference clock within the PPM threshold status signal.
      7. Monitor rx_is_lockedtoref bit is set to 1, indicating CDR is frequency locked to reference clock within the PPM threshold.
      8. Monitor rx_is_lockedtodata bit is set to 1, indicating indicates that the CDR is in locked-to-data mode.
      9. Monitor tx_clkout_freq_valid bit is set to 1, indicating TX clock out frequency is within the upper and lower limits as expected in the definition file.
      10. Monitor rx_clkout_freq_valid bit is set to 1, indicating RX clock out frequency is within the upper and lower limits as expected in the definition file.
      11. Monitor verifier_lock bit is set to 1, indicating a lock to the RX data pattern after successfully predicting 16 consecutive patterns in RX data.
      12. Monitor verifier_error bit is not set to 1. If 1, this indicates the RX data is different than the expected result.
  4. To switch profiles use step 3. and repeat step 4.
  5. Analyze the results, a passing testbench displays the following messages in the simulation window, Test case Passed and Simulation Passed, as shown in the following figure.
    Figure 97. Sample Results for the Reconfigurable PHY Example Design Testbench
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